Provably complete hardware trojan detection using test point insertion

Abstract

This paper proposes a novel minimal test point insertion methodology that provisions a provably complete detection of hardware Trojans by noninvasive timing characterization. The objective of test point insertion is to break the reconvergent paths so that target routes for Trojan delay testing are specifically observed. We create a satisfiability-based input vector selection for sensitizing and characterizing each single timing path. Evaluations on benchmark circuits demonstrate that the test point-based Trojan detection can cover all circuit locations and can detect Trojans accurately with less than 5% performance overhead.

Advancing the state-of-the-art in hardware Trojans design

“…Nefarious designs have also been deployed and detected in wireless communications devices [16]. Recent works have mostly focused on detection [17] and identification schemes [18], which assess to what extent the pieces of hardware may be vulnerable, and how related trojans can be classified. State of the art HT detection schemes include UCI [2], VeriTrust [5], FANCI [6] and DeTrust [8].…”

Aging-based leakage energy reduction in FPGAs

“…In other words, the problem becomes how to determine the input vectors for an IC that set the inputs of specific gates to specific signals. We note that this problem can be formulated as an input vector selection problem similar with that in [21]: Aging Input Vector Selection Problem. Given an IC that has N gates, where each gate i (i = 1...N ) has a required set of signals for its inputs, the aging input vector selection problem aims to find the primary input vector of the IC that satisfies the signal requirements of the N gates.…”

“…Similar with [21], we note that the aging input vector selection problem can be translated to a SAT problem, where the signal of each gate is represented by a Boolean expression concerning the primary input signals. By evaluating all the Boolean expressions (i.e., clauses) to be true simultaneously, the SAT problem aims to search for the corresponding primary input vectors, namely aging input vectors.…”

Malicious circuitry detection using fast timing characterization via test points

“…Gate-level Characterization (GLC) [24][25][27] [22] is the process of identifying the process variation in the manufactured IC. The effect of process variation can be represented as a scaling factor towards the gate-level manifestational properties, such as delay.…”

“…We develop a gate-level delay characterization approach that covers all locations on the circuit for HT detection. Although the lack of observability in delay caused by reconvergences, as shown in Figure 1, can be addressed by inserting additional test points (i.e., flip-flops) [22], we argue that the problem of identifying all the reconvergent points is 978-1-4799-0601-7/13/$31.00 c 2013 IEEE NP-complete, which cannot scale to large designs. In order to solve this issue, we employ a circuit partition method to scale down the problem space to a limited number of nonoverlapping regions.…”