Abstract:This report describes a proposed architecture for a massively parallel, shared memory computer, using commercially available microprocessors (DEC Alphas). The architecture is scalable from 4 processors to 65536 processors. Each processor has a peak performance of 200Mflops, and therefore this proposed architecture allows us to build systems with peak performance greater than 10 Tflops. Four processors are organized as a tightly coupled multiprocessing cluster. Multiple clusters (up to 8) can share a host, and … Show more
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