Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays

Marukame, Takao; Nomura, Kumiko; Matusmoto, Mari; Takaya, Satoshi; Nishi, Yoshifumi

doi:10.1109/iscas.2018.8351298

Cited by 10 publications

(3 citation statements)

References 24 publications

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“…After selecting a suitable NN architecture, the NN needs to be trained to find synaptic weights that generalize well to incoming data as well as parameter variations. A few possibilities have been proposed, such as training with random noise added to the input of each layer [13] or adding noise to the weights during training [27], [28]. Adding noise to the NN works well in reducing device overfitting by maximizing the buffer surrounding the decision boundary, much like support vector machines.…”

Section: Chaos Training To Reduce Chaosmentioning

confidence: 99%

Best Practices for Designing and Training Neural Networks Subjected to Random Variations

Janke

Anderson

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Section: Chaos Training To Reduce Chaosmentioning

confidence: 99%

Best Practices for Designing and Training Neural Networks Subjected to Random Variations

Janke

Anderson

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…To enable high-density crossbar implementation, without accuracy loss, the devices have to (1) be small, (2) require low power for read and write operations and (3) be stable [25]. PCM [92,175] and metal oxide resistive devices [51,119,146] are good candidates to (1) and (2) because their power consumption decreases along with their size. However, at small scale, they do not meet the third requirement yet, which drastically limits their use as neural network algorithm accelerators.…”

Section: Crossbar Array With Memristive Devicesmentioning

confidence: 99%

Spiking Neural Networks Hardware Implementations and Challenges

Bouvier

Valentian

Mesquida

et al. 2019

J. Emerg. Technol. Comput. Syst.

179

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Neuromorphic computing is henceforth a major research field for both academic and industrial actors. As opposed to Von Neumann machines, brain-inspired processors aim at bringing closer the memory and the computational elements to efficiently evaluate machine-learning algorithms. Recently, Spiking Neural Networks, a generation of cognitive algorithms employing computational primitives mimicking neuron and synapse operational principles, have become an important part of deep learning. They are expected to improve the computational performance and efficiency of neural networks, but are best suited for hardware able to support their temporal dynamics. In this survey, we present the state of the art of hardware implementations of spiking neural networks and the current trends in algorithm elaboration from model selection to training mechanisms. The scope of existing solutions is extensive; we thus present the general framework and study on a case-by-case basis the relevant particularities. We describe the strategies employed to leverage the characteristics of these event-driven algorithms at the hardware level and discuss their related advantages and challenges.

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“…The research associated with neuro-chips is further classified into three main methods: fully analog, fully digital, and mixed analog/digital methods. For the mixed analog/digital [ 19 , 20 ], there are two operational modes; one is neuron mode, and another is synapse mode. For the neuron mode, usually, the asynchronous digital is adopted to perform the spiking.…”

Section: Introductionmentioning

confidence: 99%

A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications

Kumar

Yingge

Ali

et al. 2022

Sensors

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This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

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Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays

Cited by 10 publications

References 24 publications

Best Practices for Designing and Training Neural Networks Subjected to Random Variations

Best Practices for Designing and Training Neural Networks Subjected to Random Variations

Spiking Neural Networks Hardware Implementations and Challenges

A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications

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