PROPHID: a heterogeneous multi-processor architecture for multimedia

Leijten, J.; Meerbergen, J. van; Timmer, A.H.; Jess, J.A.G.

doi:10.1109/iccd.1997.628864

Cited by 20 publications

(10 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The scheduler is adapted to a specific application and does not distinguish different stream types. The Prophid architecture [11] [17] by Meerbergen et al describes a dynamic RAM scheduler for the Prophid DSP platform that is focused on streams using large FIFO buffers and round-robin scheduling. Prabhat Mishra et al [12] provide optimization heuristics for known memory access patterns of a single processor.…”

Section: Related Workmentioning

confidence: 99%

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

Heithecker

Ernst

2005

Proceedings. 42nd Design Automation Conference, 2005.

View full text Add to dashboard Cite

Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.

show abstract

Section: Related Workmentioning

confidence: 99%

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

Heithecker

Ernst

2005

Proceedings. 42nd Design Automation Conference, 2005.

View full text Add to dashboard Cite

show abstract

“…To accommodate ever increasing demand of applications and for the ease of scalability, multiprocessor systems-on-chip (MPSoCs) are becoming the obvious design choice in current and future technologies [4]. To meet the strict timing requirement of multimedia applications, system designers are resorting to heterogeneous architectures [22] because of the area and power penalties associated with homogeneous cores and GPP [12].…”

Section: Introductionmentioning

confidence: 99%

A design flow for partially reconfigurable heterogeneous multi-processor platforms

Jiashu

Das

Kumar

2012

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)

View full text Add to dashboard Cite

Abstract-Modern multiprocessor systems-on-chip (MPSoCs) are expected to handle multi-application usecases. As the number and complexity of these applications scale, resource allocation to meet the application throughput requirement is becoming quite a challenge. In this paper, a complete design flow is proposed for partially reconfigurable heterogeneous MPSoC platforms. The proposed flow determines the minimum resources required to map and guarantee the throughput of applications in all use-cases. Further, a suitable mapping for each application is chosen so that energy consumption is minimized. Experiments conducted with a set of synthetic benchmarks and real-life applications clearly demonstrate the advantage of our approach over homogeneous or fully reconfigurable designs. The proposed design flow achieves more than 50% energy savings when the number of configurations is not optimized. With configurationoptimization, our flow results in 75% reduction in the number of configurations with 5% reduction in energy.

show abstract

“…Leijten et al [13] have proposed PROPHID multiprocessor architecture. This architecture essentially consists of a general purpose processor for control oriented processes, a number of application domain specific (ADS) processors and FIFO buffers for communications.…”

Section: Introductionmentioning

confidence: 99%

Automatic synthesis of system on chip multiprocessor architectures for process networks

Dwivedi

Kumar

Balakrishnan

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

View full text Add to dashboard Cite

In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.

show abstract

PROPHID: a heterogeneous multi-processor architecture for multimedia

Cited by 20 publications

References 11 publications

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

A design flow for partially reconfigurable heterogeneous multi-processor platforms

Automatic synthesis of system on chip multiprocessor architectures for process networks

Contact Info

Product

Resources

About