Properties of gold in silicon

Bullis, W Murray

doi:10.1016/0038-1101(66)90085-2

Cited by 308 publications

(95 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Diffusion of gold into bulk silicon at our VLS growth temperatures of 1000-1050°C leads to carrier lifetimes of Ͼ1 ns, 17 which combined with carrier mobilities expected for the observed dopant densities, 13,18 indicates minority carrier diffusion lengths of ജ1 m. This is in agreement with our near-field scanning optical microscope measurements of the minority carrier diffusion length of Aucatalyzed Si wires. 13 As shown in the present work, photolithography is an ideal method for enabling uniform arrays of wires of this diameter to be grown over large areas.…”

supporting

confidence: 88%

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Kayes

Filler

Putnam

et al. 2007

Applied Physics Letters

285

273

View full text Add to dashboard Cite

Arrays of vertically oriented Si wires with diameters of 1.5 m and lengths of up to 75 m were grown over areas Ͼ1 cm 2 by photolithographically patterning an oxide buffer layer, followed by vapor-liquid-solid growth with either Au or Cu as the growth catalyst. The pattern fidelity depended critically on the presence of the oxide layer, which prevented migration of the catalyst on the surface during annealing and in the early stages of wire growth. These arrays can be used as the absorber material in novel photovoltaic architectures and potentially in photonic crystals in which large areas are needed. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2779236͔Photovoltaic devices designed to achieve high cell efficiency with low-quality materials must have optically thick absorber layers, yet must simultaneously allow efficient collection of low diffusion length charge carriers. An attractive approach involves an array of vertically aligned semiconducting wires to enable carrier collection in the wires' radial direction, a distance that is short relative to their optical thickness ͑i.e. length͒.1 Well-defined wire arrays have been produced using lithographic patterning followed by anisotropic etching, 2,3 but such methods require large areas of high-quality substrate materials. In contrast, wires of various materials 4 have also been grown 'bottom up' by the vaporliquid-solid ͑VLS͒ process.5 Control of the size and position of VLS-grown wires has been demonstrated, 6,7 particularly in the case of Si by patterning of a surface oxide.8-10 Wire array growth, however, has only been achieved over relatively small areas, unless a template is used.11 We demonstrate herein the VLS growth of arrays of Si wires having diameters of 1.5 m and lengths of Ͼ70 m, with very low defect densities, over areas Ͼ1 cm 2 , without the use of a template.Attempts to grow Si wire arrays did not yield high pattern fidelity when the catalyst was not confined. Wires were grown by photolithographically patterning S1813 photoresist ͑Microchem͒ on a clean Si͑111͒ wafer, then exposing it for 5 s to buffered HF͑aqueous͒ ͑Transene, Inc., 9% HF, 32% NH 4 F͒, followed by evaporation of 500 nm of Au and lift-off of the resist. This produced a square array of 3 m diameter Au islands with a center-to-center pitch of 7 m. Samples were then annealed in a tube furnace at 900-1000°C for 20 min under 1 atm of H 2 at a flow rate of 1000 SCCM ͑SCCM denotes cubic centimeters per minute at STP͒, followed by wire growth under 1 atm of H 2 and SiCl 4 , at flow rates of 1000 and 20 SCCM, respectively. This produced arrays of low fidelity, with no control over the wire diameter or wire position ͑not shown͒. Examination of the samples after a 20 min H 2 anneal only revealed that this behavior was due to substantial agglomeration of the catalyst ͑Fig. 1͒.The successful production of large-area Si wire arrays involved the use of an oxide buffer layer to confine the VLS catalyst to the desired areas in the pattern. To implement this approach, a 300 nm oxide was ther...

show abstract

supporting

confidence: 88%

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Kayes

Filler

Putnam

et al. 2007

Applied Physics Letters

285

273

View full text Add to dashboard Cite

show abstract

“…This is expected, since Au forms a deep level trap within Si [10] while Ni remains relatively inert as long as it does not form a pre cipitate [12). This is encouraging from a photovoltaics perspective, given the difference between the abundance and costs of Au vs. Ni.…”

Section: Methodsmentioning

confidence: 81%

Single-nanowire Si solar cells

Kelzenberg

Turner-Evans

Kayes

et al. 2008

2008 33rd IEEE Photovolatic Specialists Conference

View full text Add to dashboard Cite

Solar cells based on arrays of CVD-grown Si nano-or micro-wires are being considered as a potentially low-cost route to implementing a vertical multijunction cell design via radial p-n junctions. This geometry has been pre dicted to enable efficiencies competitive with planar mul ticrystalline Si designs, while reducing the materials and processing costs of solar cell fabrication [1]. To further assess the potential efficiency of cells based on this de sign, we present here experimental measurements of mi nority carrier diffusion lengths and surface recombination rates within nanowires via fabrication and characterization of single-wire solar cell devices.Furthermore, we con sider a potential Si wire array-based solar cell design, and present device physics modeling of single-wire photo voltaic efficiency. Based on experimentally observed dif fusion lengths within our wires, we model a radial junction wire solar cell capable of 17% photovoltaic energy con version efficiency.

show abstract

“…3). This low carrier concentration in the Si:Au layer is believed to be caused by the self-compensation due to the ionization of deep acceptor and donor trap levels of substitutional gold in silicon 41,52,53 . The resulting full depletion of the Si:Au causes the majority of the applied reverse bias voltage to drop across this layer, thereby facilitating carrier transport via drift.…”

Section: Discussionmentioning

confidence: 99%

Room-temperature sub-band gap optoelectronic response of hyperdoped silicon

et al. 2014

View full text Add to dashboard Cite

Room-temperature infrared sub-band gap photoresponse in silicon is of interest for telecommunications, imaging and solid-state energy conversion. Attempts to induce infrared response in silicon largely centred on combining the modification of its electronic structure via controlled defect formation (for example, vacancies and dislocations) with waveguide coupling, or integration with foreign materials. Impurity-mediated sub-band gap photoresponse in silicon is an alternative to these methods but it has only been studied at low temperature. Here we demonstrate impurity-mediated room-temperature sub-band gap photoresponse in single-crystal silicon-based planar photodiodes. A rapid and repeatable laser-based hyperdoping method incorporates supersaturated gold dopant concentrations on the order of 10 20 cm À 3 into a single-crystal surface layer B150 nm thin. We demonstrate room-temperature silicon spectral response extending to wavelengths as long as 2,200 nm, with response increasing monotonically with supersaturated gold dopant concentration. This hyperdoping approach offers a possible path to tunable, broadband infrared imaging using silicon at room temperature.

show abstract

Properties of gold in silicon

Cited by 308 publications

References 40 publications

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Single-nanowire Si solar cells

Room-temperature sub-band gap optoelectronic response of hyperdoped silicon

Contact Info

Product

Resources

About

Properties of gold in silicon

Cited by 308 publications

References 40 publications

Growth of vertically aligned Si wire arrays over large areas (&gt;1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (&gt;1cm2) with Au and Cu catalysts

Single-nanowire Si solar cells

Room-temperature sub-band gap optoelectronic response of hyperdoped silicon

Contact Info

Product

Resources

About

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts