Propagation Delay Variation due to Process Induced Threshold Voltage Variation

Abstract

Process variation has emerged as a major concern in the design of circuits including interconnect pipelines in current nanometer regime. Process variation results in uncertainties of circuit performances such as propagation delay, noise and power consumption. Threshold voltage of a MOSFET varies due to changes in oxide thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of threshold variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced threshold variations on circuit delay is discussed for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

Monte Carlo analysis of propagation delay due to process induced line parasitic variations in VLSI interconnects

“…These results which can also be noticed in Fig. 3 are in sharp contrast to observations made in previous research works related to process variations in oxide thickness [13], driver width [14], and threshold variations [15]. Previously, it was observed that in presence of significant variations of device model parameters the variations in performance parameter such as delay is severely affected.…”

Monte Carlo Analysis of Propagation Delay Deviation due to Process Induced Line Parasitic Variations in Global VLSI Interconnects

“…It is clearly observed that the variation in propagation delay is almost same for all process technologies of 130nm, 70nm and 45nm. These results which can also be noticed in figure 3, are in sharp contrast to observations made in previous research works related to process variations in oxide thickness [13], driver width [14], and threshold variations [15]. Previously, it was observed that in presence of significant variations of device model parameters the variations in performance parameter such as delay is severely affected.…”

Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

“…These results which can also be noticed in Fig. 5, are in sharp contrast to observation made in previous research works related to process variations in oxide thickness [30], driver width [31], and threshold variations [32]. Previously, it was observed that in presence of significant variations of device model parameters, the variations in performance parameter such as delay was severely affected.…”