Programming models for hybrid FPGA-cpu computational components: a missing link

Andrews, Davıd L.; Niehaus, D.; Jidin, Razali; Finley, Melissa R.; Peck, W.; Frisbie, Matt; Ortiz, Jorge; Komp, Ed; Ashenden, Peter J.

doi:10.1109/mm.2004.36

Cited by 91 publications

(59 citation statements)

References 8 publications

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“…The ReconOS project [3] introduced an execution environment that extends the POSIX multithreaded programming model from the SW domain to reconfigurable hardware. Also, the "HybridThreads" project [2] focused on implementing the synchronization primitives provided by the POSIX multithreaded programming model (e.g. semaphores, mutexes, etc.)…”

Section: A Related Research Into Accelerator/os Integrationmentioning

confidence: 99%

“…The additional OS support provided by FUSE allows existing SW synchronization mechanisms in the OS to support HW/SW task synchronization in comparison to "HybridThreads" [2]. FUSE also incorporates the idea of tasks as units of execution across the HW boundary but, unlike [2] and [3], is not integrated with a specific programming model (e.g.…”

Section: B Comparison Between Fuse and Previous Workmentioning

confidence: 99%

“…FUSE also incorporates the idea of tasks as units of execution across the HW boundary but, unlike [2] and [3], is not integrated with a specific programming model (e.g. Pthreads).…”

Section: B Comparison Between Fuse and Previous Workmentioning

confidence: 99%

“…By extending OS support to include HW accelerators, the low-level HW interaction details can also be masked, facilitating the development of applications that use HW accelerators. Traditionally, this requires redesigning and recompiling the OS kernel for each new HW accelerator [2]. Instead, we propose customizing the OS at runtime to support existing HW accelerators as additional computing resources for SW designers, allowing the OS to automatically schedule the application(s) to leverage them.…”

Section: Introductionmentioning

confidence: 99%

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FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators

Ismail

Shannon

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-SoCs can be implemented on a single FPGA, offering designers a unique opportunity for Embedded Systems. Instead of defining a fixed architecture early in the design process, the reconfigurable platform allows architectural redesign to meet the system's specific needs. However, the ability to instantiate new modules in the reconfigurable hardware provides a unique set of challenges for integration, particularly to the software (SW) designer. Specifically, the Operating System (OS) cannot automatically abstract these platform changes without redesign.In this paper, we present FUSE, a framework for HW accelerator abstraction that provides: 1) transparency to the SW designer at the application level; and 2) OS support for easy HW accelerator integration. We illustrate FUSE as an API for an embedded Linux OS with POSIX threads on Xilinx's MicroBlaze on a Virtex5. For three different applications and HW accelerators, we achieve performance speedups ranging from 6.4-37x.

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Section: A Related Research Into Accelerator/os Integrationmentioning

confidence: 99%

Section: B Comparison Between Fuse and Previous Workmentioning

confidence: 99%

“…FUSE also incorporates the idea of tasks as units of execution across the HW boundary but, unlike [2] and [3], is not integrated with a specific programming model (e.g. Pthreads).…”

Section: B Comparison Between Fuse and Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators

Ismail

Shannon

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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“…By means of these mechanisms, the OS can suspend execution of the task at any time and then start it from the point where it was previously stopped. While these mechanisms have been known in software for a long time, corresponding functionality for the HW task [1]/thread [2] is a new topic and a matter of debate.…”

Section: Introductionmentioning

confidence: 99%

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Jozwik

Tomiyama

Honda

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYModern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

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