Programming models and HW-SW interfaces abstraction for multi-processor SoC

Jerraya,; Bouchhima,; Petrot,

doi:10.1109/dac.2006.229246

Cited by 13 publications

(12 citation statements)

References 9 publications

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“…From the point of view of software application design, there have been identified 5 concepts which are integrated in the programming model [1]. These concepts are: concurrency, threading, mapping, communication and synchronization and define 4 abstracted levels (parallel level, thread level, process level and network level) which are shown in the figure 4.…”

Section: Hardware-software Co-design Methodsmentioning

confidence: 99%

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A new Hw/Sw co-design method for multiprocessor system on chip applications

Nita

Lazarescu

Constantinescu

2009

2009 International Symposium on Signals, Circuits and Systems

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Our goal in this paper is to simulate the behavior of multiprocessor system on chip. We used an open virtual platform -OVPSim made by Imperas Company, which offers the possibility of programming and running application on the platforms architectures. With this platform we simulated both hardware architectures and running software applications. We used two types of processors -ARM7 IP core and MIPS32 IP core, shared memory, local memory and BUS for interconnections and simulated three systems on chip models and for each architecture we simulated the running of the same applications.I.

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Section: Hardware-software Co-design Methodsmentioning

confidence: 99%

“…This can cover the functionality of software low levels and also of a CPU subsystem. The use of the high level parallel programming model allows new methods of architecture optimizing and exploring [1].…”

Section: Introductionmentioning

confidence: 99%

A new Hw/Sw co-design method for multiprocessor system on chip applications

Nita

Lazarescu

Constantinescu

2009

2009 International Symposium on Signals, Circuits and Systems

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“…A single model for HW and SW based on TTL, is the differentiating factor of our approach. TTL is based on previous Philips work [7] [8].…”

Section: Related Workmentioning

confidence: 99%

System-level design flow based on a functional reference for HW and SW

Tibboel

Reyes

Klompstra

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Heterogeneous MPSoC design where flexible programmable cores are combined with optimized HW co-processors is a quite complex and challenging task. In this paper, we present a systemlevel design flow that uses a single functional reference for modeling both HW and SW. The models follow an interfacecentric design approach based on the TTL interface (Task Transaction Level). TTL models are applied at all three abstraction levels of the design flow: functional, architecture and implementation level. The TTL model at the functional level serves as the functional reference. HW implementations are generated from refined TTL models by behavioral synthesis tooling. Likewise, SW implementations are supported by source code transformations. Both the HW and SW implementations are verified against the functional reference. Details of the complete flow are presented in the paper through an MP3 case study.

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“…Both the concept of virtual architecture [6,20] and virtual processing unit (VPU) [8] allow to simulate the processor at a very high abstraction level by providing an API for OS calls and native code execution. This approach is very suitable for early design space exploration without the need for detailed simulation.…”

Section: Related Workmentioning

confidence: 99%

HySim

Kraemer

Gao

Weinstock

et al. 2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7× to 72× can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.

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Programming models and HW-SW interfaces abstraction for multi-processor SoC

Cited by 13 publications

References 9 publications

A new Hw/Sw co-design method for multiprocessor system on chip applications

A new Hw/Sw co-design method for multiprocessor system on chip applications

System-level design flow based on a functional reference for HW and SW

HySim

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