Programmable lowpower implementation of the HEVC Adaptive Loop Filter

Abstract

The Adaptive Loop Filter (ALF) is a subjective and objective image quality improving filter in the High Efficiency Video Coding standard (HEVC). The ALF has shown to be computationally complex and its complexity has been reduced during the HEVC development process. In the HEVC Test Model HM-7.0 ALF is a 9×7 cross + 3×3 square shaped filter.This paper presents a programmable application specific instruction processor for the ALF. The proposed processor processes 1920×1080p luminance frames at 30 frames per second, when operated at a clock frequency of 311 MHz. Low power consumption and a low gate count make the proposed processor suitable for embedded devices. The processor program code is written in pure C-language, which allows versatile use of the circuit and updates to the filter functionality without modifying the processor design. To the authors' best knowledge this is the first programmable solution for ALF on embedded devices.

Fine-Grained Region Adaptive Loop Filter for Super-Block Video Coding

“…Matsumura et al [17] adopted a non-local mean filter (NL-MF) to reduce the HEVC compression artifacts, where NL-MF took the weighted average of non-local similar patches. Hautala et al [18] introduced a programmable hardware design of ALF for HEVC on embedded devices, where it could support the versatile use of circuits for the filter functionality without modifying the processor design. Han et al [19] proposed a quadtree-based non-local Kuan's filter for HEVC, where the non-local similar patches are used to jointly remove the quantization noise.…”

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

“…With any adaptive filter, there is a requirement for a programmable filter, which is a primary reason behind the increasing dominance of digital instead of analog system implementations. In applications such as multi-rate decimation [6], discrete cosine transform [7], [8], channelization [9], [10], high efficiency video coding (HEVC) [11], wide bandwidth photonic filter [12] and high-rate communication [13], the filter coefficients need to be run-time reconfigurable by the error feedback signal or adaptable to varying filtering specifications in real time. To reduce the throughput rate from N clock cycles to one clock cycle, the weighted sum of the past and present input samples with changing coefficient values in an N-tap adaptive filter is implemented on field programmable gate array (FPGA) with N multiply-and-accumulate (MAC) units [14]- [17].…”

“…In [16], a dot-product unit is designed using the multiplier core on FPGA and a mechanism to reallocate the partial products for better resource utilization is proposed. As multipliers are much slower and consume substantially more area than adders, programmable filter raises the cost and latency of the system, as exemplified by the dominating complexity of coefficient computation in channel equalization [10] and the HEVC decoding time contributed by the adaptive loop filter [11].…”