Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

Abstract

Novel design algorithm for low complexity programmable FIR filters based on extended double base number system. IEEE transactions on circuits and systems I : regular papers, 62(1), 224-233.

Design of Finite Impulse Response Filter Architecture using Wallace Tree Multipliers

“…Chen, and W. Ding [1] have been proposed the concept of FIR Filter with low power based on multipliers and adders. This proposed method includes low power multiplier, RCA adder, modified booth multiplier, and shift and add multipliers, breakdown transformation in architecture of linear phase and applied to filters for consumption of power.…”

Double-Base Number System and Its Application in FIR Filter Design

“…The subexpression "101" with two adjacent nonzero powerof-two terms in binary and CSD representations and its negation corresponding to the decimal integers 5 and 5 are also frequently encountered. To incorporate this additional common subexpression, the authors of [19] proposed to extend the DBNS to include the next prime integer 5 as a choice for the second base. To differentiate it from the accustomed form of DBNS defined in [36] with 2 and 3 as the only base numbers, this form of DBNS is called the Extended Double Based Number System (EDBNS) [19], whose subset is DNBS when the second base is fixed as 3, as shown in Fig.…”

“…However, this may also result in a larger set of distinct power-of-b integers to guarantee that the ECDBNS exists for all the w-bit integers. When adopting EDBNS to design programmable FIR filter, a good trade-off is made by the following rule proposed in [19].…”

“…As the cardinality of F min stops to shrink with increasing T, the reduction in the quantity and 14 Search algorithm for the quasi-minimum EDBNS [19] bit width of adders required to realize the distinct power-of-b terms in F min ceases. Further increment of T will only increase the redundancies of one or more EDBNS representations for all w-bit integers.…”

“…Design of dedicated hardware optimized for a fixed coefficient set can then be automated to meet the stringent goals of sampling rate and power budget but at reduced flexibility and scalability. For applications that require the flexibility of multi-services on single expandable platform, the FIR filters need to be made reconfigurable and their design is more complex than fixed coefficient filters [15][16][17][18][19]. Fast reconfigurable Field Programmable Gate Arrays (FPGAs), such as the recent Virtex FPGA family [20], can be a good implementation platform for programmable filters.…”