Design of Finite Impulse Response Filter Architecture using Wallace Tree Multipliers

Abstract

Finite impulse response (FIR) filter is one of the main key mechanisms in any communication systems. The output of the system is relates to the FIR filter, so need to design an efficient FIR filter, to get a perfect output. Filter design contains many blocks; one of the main blocks is multiplier. Many types of multipliers are available in the digital circuits, but need an efficient multiplier design to get better filters. Multiplier is one of the basic building blocks in the digital circuits. So the performance of the multiplier is important to get an efficient circuit design. Power consumption is one of the major drawbacks in the multiplier. Power consumed by the multiplier is higher in the digital circuits. Wallace tree multiplier was designed and implemented using verilogHDL. This multiplier reduces the stages of partial product addition. So this multiplier takes less number of gates to implement and also it overcomes the existing multiplier drawbacks. Finally the designed multipliers are applied into the FIR filter, and show the best filter.