Programmable Conductance Switches for FPAAs

Abstract

Floating gate transistors make excellent switches for large-scale field-programmable analog arrays (FPAAs). In addition to simple "on" and "off" connections, they can be used as computational elements within synthesized circuits. However, the programmable range of these computational elements as well as the quality of an "on" switch can be limited by the particular switch topology and programming methods. To extend the useful range of floating gate switches, programming method improvements and indirectly programmed topologies are explored and demonstrated. I. FPAA SWITCHESSwitches are one of the most important components of reconfigurable systems. In field-programmable analog arrays (FPAAs), they generally are the limiting factor in device bandwidth, and therefore many researchers have attempted to improve upon basic switch designs through various means. Interconnections have been made using fuses, antifuses [1], and even parallel G M cells [2] that use active components as computational elements and interconnects. However, all of these interconnect strategies involve simple "on" or "off" connections between components.In addition to good "on" switches, the floating gate interconnects in large-scale FPAAs [3] can be used as computational elements within the synthesized circuits by programming them between "off" and "on" states. Normally switches are computationally useless and consume a significant amount of the reconfigurable device area, especially when considering the memory elements used to control them. Using floating gate switches as programmable conductances can increase the computational utilization of the reconfigurable device area by implementing current sources, voltage references, and even larger circuits such as diffusors and multipliers within the switch fabric. Common floating gate transistor arrays and their associated programming methods [4] can limit the range and effectiveness of computational switch elements. However, modifications to these methods and topologies can significantly reduce these limitations. II. FLOATING GATE TRANSISTOR SWITCHESThe floating gate switch is simply a pFET with capacitive gate coupling, as shown in Fig. 1. A double poly capacitor is used to couple a control voltage, V C , to the floating gate, and a MOS capacitor is used as a tunneling junction. With no DC path to a fixed potential, charge can be stored on the floating node. The current flowing through the floating gate pFET is then controlled by the voltages coupled onto the floating gate and the amount of charge stored on the floating node. ByFig. 1. Floating gate pFET layout. 0 0.5 1 1.5 2 10 −10 10 −9 10 −8 10 −7 10 −6 10 −5 10 −4 V C (V) I D (A) "on" s witch "off" switch inject tunnel + -A V C + -V DD Fig. 2. Injection and tunneling of floating gate transistors.modifying this charge, the transistor can be programmed over a wide range of values for a given set of terminal voltages.Fowler-Nordheim tunneling is used as a global erase for the array of floating gate pFET switches, which can be viewed as an increase ...

Neural Dynamics in Reconfigurable Silicon

“…The programmable switch matrix used in the earlier FPAA [108] used the application of high gate voltage or high drain voltage as the method of isolation while the selected device had a low voltage at both the gate and drain terminals. However this method has a number of disadvantages, the primary one being over-injection of devices beyond the isolation point [109]. This IC employs the superior source-side selection [109] coupled with indirect programming [42] to achieve impressive isolation while not sacrificing the quality of an ON switch.…”

“…However this method has a number of disadvantages, the primary one being over-injection of devices beyond the isolation point [109]. This IC employs the superior source-side selection [109] coupled with indirect programming [42] to achieve impressive isolation while not sacrificing the quality of an ON switch. Figure 29(a) shows the architecture of one switch element that occupies 13×6 µm 2 .…”

Parasitic charge movement in floating-gate array programming

“…The most direct way to modify the array element in Figure 1b would be to place a switch on the drain of the FG-pFET in order to shield it from the injection pulse. In [9], the use of additional selection circuitry is discussed in the context of array isolation, and switches on either the source or drain of a FGpFET are considered. The findings of the work can be augmented in light of the data herein.…”