Profile guided selection of ARM and thumb instructions

Krishnaswamy, Arvind; Gupta, Rajiv

doi:10.1145/513837.513840

Cited by 20 publications

(41 citation statements)

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“…The best known examples of these mixed-width instruction sets are MIPS with MIPS16 [Kissell 1997] and ARM with Thumb [Turley 1995]. Recently, Krishnaswamy and Gupta [2002] proposed an automated profile-guided technique to select ARM/Thumb code. When combined with Thumb extensions [Krishnaswamy and Gupta 2005] that increase its performance, these techniques can avoid the need to compromise between performance and code size.…”

Section: Mixed-width Instruction Setsmentioning

confidence: 99%

Link-time binary rewriting techniques for program compaction

Sutter

Bus

Bosschere

2005

ACM Trans. Program. Lang. Syst.

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Small program size is an important requirement for embedded systems with limited amounts of memory. We describe how link-time compaction through binary rewriting can achieve code size reductions of up to 62% for statically bound languages such as C, C++, and Fortran, without compromising on performance. We demonstrate how the limited amount of information about a program at link time can be exploited to overcome overhead resulting from separate compilation. This is done with scalable, cost-effective, whole-program analyses, optimizations, and duplicate code and data elimination techniques. The discussed techniques are evaluated and their cost-effectiveness is quantified with SQUEEZE++, a prototype link-time compactor.

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Section: Mixed-width Instruction Setsmentioning

confidence: 99%

Link-time binary rewriting techniques for program compaction

Sutter

Bus

Bosschere

2005

ACM Trans. Program. Lang. Syst.

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“…Note that the battery dissipation of a program is a compositional effect caused by both the program's energy consumption and the characteristics of the battery itself. Previous work [22,23,14,21,15] has studied the power consumption characteristics at the processor instruction level. Combined these with battery models [7,3,10,19,18,17,20], one can estimate the battery dissipation of a program.…”

Section: Application-level Power Predictionmentioning

confidence: 99%

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. niques select instructions based on their energy consumption [14,22,23,21].…”

Section: Introductionmentioning

confidence: 99%

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Application-level prediction of battery dissipation

Krintz

Wen

Wolski

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…Different researches have been proposed to cope with this problem. Profile guided compiler heuristics at function level granularity have been proposed in [9] to determine which code, from the two available, maximizes the code size reduction without causing a significant loss in performance. Halambi et.al.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Canedo

Abdallah

Sowa

Embedded and Ubiquitous Computing

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Abstract. Embedded systems very often demand small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a dual instruction set. This approach reduces code size at the cost of performance degradation due to the greater number of reduced width instructions required to execute the same task. We propose a novel alternative for reducing code size by using a single reduced instruction set queue machine. We present a efficient code generation algorithm to insert additional instructions to be able to execute programs in the reduced instruction set. Our experiments show that the insertion of additional instructions is minimal and we demonstrate improved code size reduction of 16% over MIPS16, 26% over Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler without any optimization is able to extract about the same parallelism than fully optimized RISC code.

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Profile guided selection of ARM and thumb instructions

Cited by 20 publications

References 0 publications

Link-time binary rewriting techniques for program compaction

Link-time binary rewriting techniques for program compaction

Application-level prediction of battery dissipation

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

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