Profile Evolution of High Aspect Ratio Silicon Carbide Trenches by Inductive Coupled Plasma Etching

Dowling, Karen M.; Ransom, Elliot; Senesky, Debbie G.

doi:10.1109/jmems.2016.2621131

Cited by 53 publications

(41 citation statements)

References 55 publications

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“…This is illustrated in Fig. 4(a) with the help of simulated potential lines in comparable SJ and CSSJ compatible with the state of the art [4], [13]. The nearly flat potential lines over WI point to negligible voltage drop across the insulator thickness.…”

Section: B1 Breakdown Voltage Of Balanced Devicesmentioning

confidence: 72%

“…The details of the device structures simulated appear in the relevant figures. The structures are compatible with the state of the art as per which the negative fixed charge NI at the insulator / semiconductor interface can be varied in the range of 2.57.9 ×10 12 cm -2 [4] and the aspect ratio of the insulator (which fills trenches) and pillars can be as high as 18 [13].…”

Section: Device Operationmentioning

confidence: 84%

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Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design

Akshay

Karmalkar

2020

IEEE J. Electron Devices Soc.

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We discuss details of the Charge Sheet SuperJunction (CSSJ) in 4H-Silicon Carbide (SiC). This device was earlier proposed in Si material. A CSSJ is obtained by replacing the p-pillar of a SJ by a bilayer insulator, e.g. Al2O3 / SiO2; the inter-layer interface of this insulator has a negative charge-sheet, whose magnitude is easily controlled via the insulator deposition temperature. This charge-sheet depletes the n-pillar. Two potential advantages of this structural modification are brought out. First, it can avoid the problems related to SiC SJ's p-pillar fabrication. Second, it can lower the specific-on resistance, RONSP, below that of SJ by 5−45 %, since SiC technology allows the insulator to be thinner than the p-pillar. The critical field, EC, in SiC is > 10 times higher than that in Si. We give an analytical breakdown voltage, VBR, model, which shows that the VBR sensitivity to charge imbalance due to inevitable process variations is inversely proportional to EC; hence, this sensitivity of CSSJ in SiC is > 10 times lower than that in Si. On the other hand, we give numerical simulations to establish that, in spite of EC differences, the SiC CSSJ inherits the advantage of upto 15% higher VBR compared to SiC SJ, from its Si counterparts. We show how our prior analytical procedure of designing a SJ can be adapted to design a CSSJ having a lower RONSP than the SJ, at a specified VBR in 1-10 kV range and charge imbalance  20 %. Our work should strengthen the motivation for fabricating the CSSJ in SiC.

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Section: B1 Breakdown Voltage Of Balanced Devicesmentioning

confidence: 72%

Section: Device Operationmentioning

confidence: 84%

Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design

Akshay

Karmalkar

2020

IEEE J. Electron Devices Soc.

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“…Optical lithography [24][25][26][27] is a parallel micro-/nanographic-imaging method that is commonly used in MEMS processing. In addition, etching process [28][29][30][31] is an important micro-/nanostructure process in MEMS and that is usually performed after lithography. Therefore, this paper investigated the direct lithography on the graphite surface via lithography to examine the stability of direct photoresist pattern imaging on the graphite surface.…”

Section: Methodsmentioning

confidence: 99%

Experiment Research on Micro-/Nano Processing Technology of Graphite as Basic MEMS Material

Zhang

Liu

et al. 2019

Applied Sciences

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Graphite is expected to be a common choice for basic microelectromechanical-system (MEMS) material in the future. However, in order to become a basic MEMS material, it is very important for graphite to be adapted to the commonly-used micro-/nanoprocessing technology. Therefore, this paper used a directly lithography and etching process to study micro-, /nanoprocessing on graphite. The results show that the graphite surface is suitable for lithography, and that different shapes and sizes of photoresist patterns can be directly fabricated on the graphite surface. In addition, the micro-meter height of photoresist could still resist plasma etching when process nanometers height of graphite structures. Therefore, graphite with photoresist patterns were directly processed by etching, and nanometer amounts of graphite were etched. Moreover, micro-/nanoscale graphite structure with height ranges from 29.4 nm–30.9 nm were fabricated with about 23° sidewall.

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“…Previously reported GaN trench depths were approximately 1-3 μm with aspect ratios of 1-3. We therefore used SiC trench structures fabricated by ICP-RIE as our reference structures [23][24][25]. In Fig.…”

Section: A Gan Trench Fabrications For Power Devicesmentioning

confidence: 99%

Photoelectrochemical Etching Technology for Gallium Nitride Power and RF Devices

Horikiri

Sato

Fukuhara

et al. 2019

IEEE Trans. Semicond. Manufact.

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Photoelectrochemical (PEC) etching was used to fabricate deep trench structures in GaN-on-GaN epilayers grown on n-GaN substrates. The width of the side etching was less than 1 µm, with high accuracy. The aspect ratio (depth/width) of a 3.3-µm-wide trench with a PEC etching depth of 24.3 µm was 7.3. These results demonstrate the excellent potential of PEC etching for fabricating deep trenches in vertical GaN devices. Furthermore, we simplified the PEC etching technology to permit its use in a wafer-scale process. We also demonstrated simple contactless PEC etching technologies for the manufacture of power and RF devices. A trench structure was fabricated in a GaN-on-GaN epilayer by simple contactless PEC etching. The role of the cathodic reaction in contactless PEC etching is discussed in relation to the application of a GaN HEMT epilayer on a semi-insulating substrate. Fortunately, the GaN HEMT structure contains an ohmic electrode that can act as a cathode in contactless PEC etching, thereby permitting the recess etching of a GaN HEMT epilayer grown on a semi-insulating SiC substrate. These results indicate that PEC etching technologies are becoming suitable for use in the fabrication of practical GaN power and RF devices.

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Profile Evolution of High Aspect Ratio Silicon Carbide Trenches by Inductive Coupled Plasma Etching

Cited by 53 publications

References 55 publications

Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design

Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design

Experiment Research on Micro-/Nano Processing Technology of Graphite as Basic MEMS Material

Photoelectrochemical Etching Technology for Gallium Nitride Power and RF Devices

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