Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip

Kim, Changgeun; Rhee, Sunwook; Kim, Juhee; Jee, Yong

doi:10.1109/iccea.2010.63

Cited by 10 publications

(1 citation statement)

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“…The concatenated coding scheme has resemblance to pseudo-product codes [6] and product codes [7]- [9], [15]. However, only few of them [8], [9] have been applied to storage devices using NAND flash memories, and to the best of our knowledge, there has not been thorough analysis of codes in this category over noisy channels characterizing MLC NAND flash memory. It will be shown that the error-control system using the concatenated code provides a competitive performance to that of a single long BCH code.…”

Section: Introductionmentioning

confidence: 99%

Concatenated BCH codes for NAND flash memories

Cho

2012

2012 IEEE International Conference on Communications (ICC)

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In this work, we consider designing high-rate errorcontrol systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger errorcorrecting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10 −14 , which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation.

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Section: Introductionmentioning

confidence: 99%