Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes -- A Graph Theoretic Approach

Datta, Rudrajit; Touba, N.A.

doi:10.1109/dft.2011.3

Cited by 19 publications

(4 citation statements)

References 11 publications

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“…When m is given, the problem comes down to find the minimal k q , which is obviously k q = 2. By solving the first quadratic equation, the optimal q opt when K and m are given is (12). □…”

Section: Appendix 1: Proof Of the Rs Code Parameters To Construct Thementioning

confidence: 99%

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Design of reliable storage and compute systems with lightweight group testing based non‐binary error correction codes

Karpovsky

Kinsy

2018

IET Computers & Digital Techniques

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In this study, the authors propose a new group testing based (GTB) error control codes (ECCs) approach for improving the reliability of memory structures in computing systems. Compared with conventional single-and double-bit error correcting codes, the GTB codes provide higher reliability at the multi-byte error correction granularity. The proposed codes are cost-efficient in their encoding and decoding procedures. Instead of requiring multiplication or inversion over Galois finite field like most multi-byte ECC schemes, the proposed technique only involves bitwise XOR operations, therefore, significantly reducing the computation complexity and latency. For instance, to correct m errors in a Q-ary codeword of length N, where Q ≥ 2, the compute complexity is mere O(mNlog Q). The GTB codes trade redundancy for encoding and decoding simplicity, and are able to achieve better code rate than other ECCs of the same trade-off. The proposed GTB codes lend themselves well to designs with high reliability and low computation complexity requirements, such as storage systems with strong fault tolerance, or compute systems with straggler tolerance, and so on.

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Section: Appendix 1: Proof Of the Rs Code Parameters To Construct Thementioning

confidence: 99%

“…Hence, interleaved codes are invented as an alternative solution. Interleaved Hamming codes [10] can be used for single‐byte error correction, and interleaved orthogonal latin square codes (OLSCs) [11, 12] usually for multi‐byte error correction. Other types of interleaved codes also exist.…”

Section: Introductionmentioning

confidence: 99%

Design of reliable storage and compute systems with lightweight group testing based non‐binary error correction codes

Karpovsky

Kinsy

2018

IET Computers & Digital Techniques

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“…These codes are one-step majority logic decodable which enables fast and parallel decoding [4]. However, OLS codes require more parity check bits than other codes that can correct the same number of errors [7]. Other one-step majority logic decodable codes that have been explored for memory protection are a class of Euclidean Geometry (EG) codes.…”

Section: Introductionmentioning

confidence: 99%

Optimized parallel decoding of difference set codes for high speed memories

Demirci

Reviriego

Maestro

2014

Microelectronics Reliability

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“…In some applications, this disadvantage is offset by their modularity and the simple and low delay decoding implementation (as OLS codes are OS-MLD). For example, OLS codes have been recently considered to protect memories [12], caches [13], and interconnections [14].…”

Section: Introductionmentioning

confidence: 99%

A Method to Extend Orthogonal Latin Square Codes

Reviriego

Pontarelli

Sánchez‐Macian

et al. 2014

IEEE Trans. VLSI Syst.

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Error correction codes (ECCs) are commonly used to protect memories from errors. As multibit errors become more frequent, single error correction codes are not enough and more advanced ECCs are needed. The use of advanced ECCs in memories is, however, limited by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an interesting option as the decoding is simple and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and have been recently considered to protect caches and memories. The main advantage of OLS codes is that they provide a wide range of choices for the block size and the error correction capabilities. In this brief, a method to extend OLS codes is presented. The proposed method enables the extension of the data block size that can be protected with a given number of parity bits thus reducing the overhead. The extended codes are also OS-MLD and have a similar decoding complexity to that of the original OLS codes. The proposed codes have been implemented to evaluate the circuit area and delay needed for different block sizes.

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Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes -- A Graph Theoretic Approach

Abstract: The paper proposes a scheme by which an Orthogonal Latin Square code (OLS)

Cited by 19 publications

References 11 publications

Design of reliable storage and compute systems with lightweight group testing based non‐binary error correction codes

Design of reliable storage and compute systems with lightweight group testing based non‐binary error correction codes

Optimized parallel decoding of difference set codes for high speed memories

A Method to Extend Orthogonal Latin Square Codes

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