Product-Oriented System-in-Package (SiP) Technology for Next Generation Wireless/Portable Electronics

Sham, Man Lung; Fu, Haley; Leung, L.W.; Chen, Y.C.; Chung, Tom

doi:10.1109/estc.2006.280014

Cited by 4 publications

(1 citation statement)

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“…Heterogeneous and homologous integration through the system in package (SiP) is one of the most important technologies for more than Moore due to its low cost and appropriate technical challenges. It can meet the requirements of consumers for electronic products, so it has been widely investigated [ 2 , 3 ].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

Chen

et al. 2022

Materials

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This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

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Section: Introductionmentioning

confidence: 99%