Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

Abstract

This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

Delamination of Plasticized Devices in Dynamic Service Environments

“…The results show that the CTE mismatch of the EMC/Si chip induces a continuous increase in shear stress and principal stress, which eventually exceeds the EMC/Si chip interface adhesion force, and interfacial delamination is unavoidable. Chen et al [ 58 ] also showed, in their research work on package warpage, that the wafer warpage can be significantly optimized by selecting EMCs with smaller CTEs and by reducing the thickness of EMC. Salahouelhadj [ 59 ], in a simulation of warpage inside FCBGA packages due to CTE mismatch of different material layers, found that the maximum warpage value of 67 μm occurs near 70 °C and 87 μm at 250 °C during heating.…”

Effective Macroscopic Thermomechanical Characterization of Multilayer Circuit Laminates for Advanced Electronic Packaging

“…To macroscopically and thermomechanically describe multimaterial and multiscale circuit laminates, the most common effective approach is the simple linear (inverse) ROM estimate [14][15][16][17][18][19], namely, the Voigt (constant strain) and Reuss (constant stress) approximations. This approach has been broadly applied in the thermal or thermomechanical characterization of RDLs [16], PCBs [20], IC substrates [21], and underfill/bump layers [22,23] in microelectronics packaging due to its simplicity and ease of implementation. Unfortunately, this approach mostly lacks accuracy because of its inability to handle the elastic heterogeneity and anisotropy of circuit laminates, which are essentially two of the leading root causes of thermally induced warpages and material failures in electronic packages.…”

Exploring the Influence of Material Properties of Epoxy Molding Compound on Wafer Warpage in Fan-Out Wafer-Level Packaging

“…Figure 2 shows a schematic diagram of the structure during the decarrier process, where "Die" represents the chip, "Si THK" represents the stop layer (silicon nitride-a high dielectric constant material), "Passivation" represents the passivation layer, "Cu-pillar" represents the copper pillar, and "epoxy molding compound (EMC)" represents the epoxy molding compound. Many previous studies [1][2][3][4][5][6][7][8][9][10][11][12][13][14] have focused on evaluating whether changes in the structural design or material selection of the packaging can reduce the amount of wafer warpage caused by the thermal process in fan-out wafer-level packaging (FOWLP). Analyzing the effect of material properties on wafer warpage is one of the important ways of understanding warpage factors and effectively improving wafer warpage.…”

“…Yang et al [5] observed that reducing the CTE mismatch between materials on either side of the neutral axis during curing process was beneficial in minimizing warpage. Chen et al [6] conducted a simulation analysis on the effect of CTE of EMC on warpage after the molding process and found that smaller CTE of EMC resulted in smaller warpage, while an increase in CTE from 7 ppm/ • C to 10 ppm/ • C led to a 60% increase in warpage. Che et al [7] analyzed the factors affecting warpage of the wafer packaged using fan-out interposer (FOI) technology.…”

“…In previous studies [1][2][3][4][5][6][7][8][9][10][11][12][13][14], analysis of the effect of material properties on warpage was mostly focused on the differences in the types of materials or the magnitude of the coefficient of thermal expansion (CTE). However, there are currently few comprehensive discussions on the various material property parameters of the EMC materials, such as Young's modulus of the EMC before the Tg between 25 • C and 35 • C (E L ) and after the Tg between 235 • C and 260 • C (E H ), the thermal expansion coefficient (α1, α2), and the temperature interval (∆T) between E L and E H .…”