Processor/memory/array size tradeoffs in the design of SIMD arrays for a spatially mapped workload

A System for Evaluating Performance and Cost of SIMD Array Designs

“…Note that for the image understanding application suite this latter factor is likely to average only a factor of 3 to 4 rather than 32 or more. This is because most of the application data types are 8-and 16-bit integers and because many operations are inherently boolean [15]. There is also less locality in instruction-level simulation: whereas several virtual machine arrays can fit in 1 MB of level 2 cache, that cannot be said of the data structures representing the contexts of each PE in the array.…”

“…This emulation can either be done entirely in software, through hardware support in the array control unit (ACU), or through a combination of the two. This process is explained in detail in [15].…”

Architectural Enhancements for Color Image and Video Processing on Embedded Systems

“…Recently, Gentile et al have presented a study to determine the impact of varying granularity of mapping an image to the PE array [33]. In [39], Herbordt et al examined the effects of varying the array size, the datapath, and the memory hierarchy on both cost and performance. However, these studies measured processing performance and efficiency on sets of grayscale (1-D) image processing applications, failing to provide a quantitative understanding of performance and efficiency with respect to 3-D vector processing for different PE configurations.…”

Array control for high-performance SIMD systems

“…Emulating interacting VPE instructions such as feedback and communication is more complex and can sometimes add significant overhead [21].…”