Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits

Abstract

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

“…2 clock IC output signal amplitudes recorded by the oscilloscope are well below the ∼ 10 V logic swing reported in 500 • C Earth-air oven testing of this same chip design [31], [32], and there are also significant differences evident between starting (0 days) and ending (60 days) amplitudes. These observations are consistent with understood behaviors seen in preceding studies of SiC JFET ring oscillator ICs [26], [27], [30], [33], [39]. It is well known that measurement probe loading effects must be considered when measuring electrical signals using an oscilloscope, especially when measuring circuits with both high output resistance and high frequency signal (as is the case for these clock ICs) [40].…”

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

“…As seen in Figure 2 characteristics, JFETs near the wafer edge exhibit substantially more negative threshold voltage V T , which results in larger on-state currents. I D vs. V G sweeps (shown elsewhere [1,6]) demonstrated complete JFET channel turn-off to less than 1/1000th of on-state current.…”

“…Given that prolonged and stable IC functionality is crictical for most applications, the JFET IC technology emphasizes extreme temperature durablity and stability over other semiconductor device performance metrics. The 500 °C durable ICs are comprised of 4H-SiC n-channel JFETs and 4H-SiC n-channel resistor primitive devices connected by two levels of conductive metal interconnect [1,[4][5][6]. A simplified cross-sectional diagram of this approach is illustrated below in Figure 1.…”

“…Experimental measurements from two successively processed JFET IC wafer runs were used for SPICE model development/verification: 76 mm diameter epitaxial "Wafer 8.1" (procured in 2008) was processed first [4,5,14], followed by 76 mm diameter epitaxial "Wafer 9.2" (procured in 2014) [1,6,14]. While the same photolithography masks were used for both wafers, Reference [6] describes all the significant differences in processing between the two wafers.…”

“…A separate submission to this conference reports fabrication and testing of 500 °C 1000+ hour durable SiC JFET ICs with two levels of metal interconnect [1]. This advance to multi-level interconnect for 500 °C durable ICs facilitates more rapid up-scaling to higher levels of complex electronic functionality in order to better meet the needs of various aerospace, automotive, energy production, and industrial systems [2,3].…”