Process variations and their impact on circuit operation

Natarajan, Suriyaprakash; Breuer, M.A.; Gupta, Sumita

doi:10.1109/dftvs.1998.732153

Cited by 63 publications

(39 citation statements)

References 9 publications

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“…Unfortunately, these parameters are interdependent and our lack of complete knowledge of this interdependence leads to uncertainty and inaccuracies in the simulation of SI loss [Wang et al 2007]. Moreover, process variations and manufacturing defects may aggravate the SI-related problems [Natarajan et al 1998]. Since it is unacceptable to over-design the circuit to tolerate signal integrity loss in all cases and it is impossible to predict the occurrence of defects, manufacturing test strategies are essential for detecting SI-related errors [Cuviello et al 1999;Sirisaengtaksin and Gupta 2002;Tehranipour et al 2003].…”

Section: Introductionmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

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Section: Introductionmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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“…(Process variation data for newer technologies are not available to us.) The percentage variations are assumed to be the same as that in the 0.8 µm process reported in [11]. The percentage variations cover 98% of all measured data points implying that process variation effects can be more severe than that reported here.…”

Section: Process Variationmentioning

confidence: 90%

“…This motivates the validation problem. The impact of process variation on noise has been discussed in [11]. The severity of the impact of process variation on noise depends on the aggressiveness of a design.…”

Section: Introductionmentioning

confidence: 99%

Validation and test generation for oscillatory noise in VLSI interconnects

Sinha

Gupta

Breuer

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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“…Permanent faults are caused by manufacturing imperfection as well as the aging effect in transistors. Transient faults, also known as soft errors, are due to high-energy particle strikes [4] and voltage droops [58]. Both types of faults are important from the perspective of system reliability.…”

Section: Afi: Application-level Fault Injectionmentioning

confidence: 99%

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Wang¹

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As the semiconductor industry keeps evolving at the pace predicted by Moore's Law, computer system architects are facing increasing challenges from the three major design constraints: performance, power, and reliability. Thermal constraints from a reasonable cooling cost do not scale well as technology evolves. The dwindling scaling on threshold voltage leads to a slower pace of supply voltage scaling. These two effects lead to an increasing power density in current and future technology generations. Reliability has emerged as a primary design constraint due to the smaller feature size and generally lower supply voltage for electronic devices. Transient errors caused by high-energy particle strike and voltage noises are expected to increase significantly in frequency.Performance improvement becomes more challenging for future architectures with limitations set by the power and the resilience constraints.Integration of accelerators to create heterogeneous processors is becoming more common for both power and performance reasons. However, this adds one more dimension to the design space that is already complex due to technology variants, system organizations, application's variability, and so on. Therefore, high-level models are essential for system designers to explore the design space and make decisions in a timely manner. Additionally, the three design constraints compete with each other. For example, resilience-aware techniques, such as DMR and TMR, are expensive in terms of power and performance, low-power designs usually come with a price of lower speed.Consequently, it requires system designers to make trade-offs by considering all the three design constraints at the same time.To address these challenges, we (1) propose an analytical modeling framework called Lumos that is capable of modeling power and performance for heterogeneous architectures with hardware iv v accelerators. Then we (2) use Lumos to explore the design space composed of CPU cores and accelerators, revealing important scaling trend for future heterogeneous architectures. We further (3) propose a rapid modeling framework to characterize resilience across a range of applications in DSP, and image processing domains; And finally we (4) propose an integrated framework to optimize energy-efficiency by trading off design constraints of power, performance and resilience. Acknowledgments

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Process variations and their impact on circuit operation

Cited by 63 publications

References 9 publications

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Validation and test generation for oscillatory noise in VLSI interconnects

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

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