Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits

Self Cite

Altering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two-input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states.Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions.

Section: Soft Error Analysismentioning

confidence: 99%

Section: Soft Error Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Impact of negative bias temperature instability on single event transients in scaled logic circuits

Shah

Waltl

2021

Self Cite

“…The three major components are: sub-threshold leakage current (I sub ), junction leakage (I jn ), and gate leakage (I g ). 32 The major leakage current components in conventional 6T SRAM cell considering "0" and "1" are stored at node Q and QB as shown in Figure 8A and given by:…”

Section: Leakage Current Estimationmentioning

confidence: 99%

“…The leakage current has three major components to describe its presence in any digital circuit when the circuit is in idle mode. The three major components are: sub‐threshold leakage current ( I sub ), junction leakage ( I jn ), and gate leakage ( I g ) 32 . The major leakage current components in conventional 6T SRAM cell considering “0” and “1” are stored at node Q and QB as shown in Figure 8A and given by:

I_{{italicsub}_{6 T}} = I_{{italicsub}_{M 5}} + I_{{italicsub}_{M 3}} + I_{{italicsub}_{M 2}}

I_{g_{6 T}} = \sum_{i = 1}^{4} ([], I_{{gs}_{Mi}}) + I_{{italicgd}_{M 6}} + I_{{italicgs}_{M 1}} + \sum_{j = 4}^{6} ([], I_{{gs}_{Mj}})

I_{{italicjn}_{6 T}} = \sum_{m = 5}^{6} ([], I_{{jns}_{Mm}}) + \sum_{n = 2}^{3} ([], I_{{jnd}_{Mn}}) + I_{{italicjnd}_{M 6}}

I_{{normalleakage}_{6 T}} = I_{{italicsub}_{6 T}} + I_{g_{6 T}} + I_{{italicjn}_{6 T}}

…”

Section: Proposed D2lp10t Sram Cellmentioning

confidence: 99%

An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Gupta

Sharma²,

Shah

et al. 2020

Self Cite

The LiFi enabled smart street lighting system requires the adaptive SoC to save huge amount of power/energy for data storage, which plays an important role for any urban area development. For the above application, an energy-efficient data-dependent power supplied 10T SRAM cell with half-select free readdecoupled circuit is designed to boost stability while stacking effect controls the leakage current against the process-voltage-temperature variations. CMOS 65 nm technology node is used for the implementation and comparison of various SRAM cells. The proposed cell offers 4×, 1.15×, and 1.66× higher read, hold, and write stability, respectively, as compared with the 6T cell at 0.4 V supply voltage. The improvement of write, read, and leakage power of the proposed 10T cell are 98.03%, 56.25%, and 91.07%, respectively, as compared with the 6T cell at 0.2 V supply. It is also observed that the proposed 10T cell has 88.88% and 85.71% write 0 and write 1 energy, respectively, as compared with the 6T cell at 0.2 V supply voltage. To better assess the cell, we introduced the figure of merit (FOM) and observed that the FOM of the proposed cell is 125× higher as compared with the 6T cell at 0.4 V supply voltage.

Design of a stable single sided 11T static random access memory cell with improved critical charge

Sachdeva

2022

Radiation-induced soft errors are becoming a key challenge in satellite-based communication. The worst-hit component of such devices is static randomaccess memory bit-cells, owing to their high density, large area, and lowoperating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge-boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft-error-immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13Â/1.38Â/0.90Â/1.04Â/1.03Â improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31Â/1.17Â/1.31Â/1.41Â/1.01Â compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97Â/0.98Â/1.91Â/1.24Â/1Â when equated to 6T/PP10T/ AS8T/Quatro10T/LC10T cell. Improved Inter-cell and Intra-cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.