Design of a stable single sided <scp>11T</scp> static random access memory cell with improved critical charge

Sachdeva, Ashish

doi:10.1002/jnm.3076

Cited by 9 publications

(5 citation statements)

References 65 publications

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“…TMDFET-based circuits are particularly attractive due to their significantly lower power consumption, primarily attributed to the minimal I OFF of TMDFETs. Both TMDFET and GNRFETbased circuits demonstrate superior performance in terms of Energy-Delay Product (EDP) when compared to alternative devices [50][51][52]. TMDFET-based circuits exhibit a slightly higher (1.02X) PDP compared to GNRFET-based circuits [49].…”

Section: Comparison With Other Gnrfet Addersmentioning

confidence: 99%

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Elangovan,

Sharma,

Sachdeva

2023

Phys. Scr.

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Owing to balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs) they a suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and Ion/Ioff ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, and low power-delay product of 43.3 nW, 0.47 pS and 0.02 x 10-18 J, respectively using 0.7 V supply voltage. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

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Section: Comparison With Other Gnrfet Addersmentioning

confidence: 99%

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Elangovan,

Sharma,

Sachdeva

2023

Phys. Scr.

Self Cite

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“…The specifications and design requirements of SRAM cells vary widely due to consistent improvements in the electronic market. The on-chip SRAM in the implemented embedded application system is a key factor in significant parameters such as access time, power dissipation, and on-chip occupied space [3]. However, in many cases, such applications are batteryoperated, and demand low-voltage operation without compromising the performance of the SRAM bit-cell.…”

Section: Introductionmentioning

confidence: 99%

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Sachdeva,

Sharma,

Bhargava

et al. 2024

Phys. Scr.

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Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read-and-hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21× and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99× compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

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“…Unlike write latency, which can be managed using buffers * Authors to whom any correspondence should be addressed. and intelligent scheduling [3][4][5], read delay is highly influenced by the inherent memory mechanism, although temperature and supply voltage exhibit widespread effects on memory characteristics [6][7][8]. Research on read delay can lead to advancements in memory design.…”

Section: Introductionmentioning

confidence: 99%

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism

Oh,

Jeon,

Shin

et al. 2024

Nanotechnology

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This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

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Design of a stable single sided 11T static random access memory cell with improved critical charge

Cited by 9 publications

References 65 publications

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism

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