Process temperature dependent high frequency capacitance-voltage response of ZrO2/GeO2/germanium capacitors

Bethge, Ole; Abermann, S.; Henkel, Christoph; Straif, Christoph J.; Hutter, Herbert; Smoliner, J.; Bertagnolli, E.

doi:10.1063/1.3295698

Cited by 17 publications

(8 citation statements)

References 15 publications

(19 reference statements)

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“…The corresponding measured data of the MOSCAPs are shown in Table I. It is noted that reliable IV and breakdown voltage measurements were hardly possible for the samples without PMA and the corresponding entries are marked by "…" in Table I. Generally, by varying the oxygen annealing temperature from 400 C to 550 C and 600 C, a large impact of temperature on CV characteristics becomes visible, reducing the D it by more than one order of magnitude from D it ¼ 3.7 Â 10 12 eV À1 cm À2 (400 C) to D it ¼ 1.24 Â 10 11 eV À1 cm À2 (550 C), and D it ¼ 9.7 Â 10 10 eV À1 cm À2 (600) C. As shown from the inversion regions of the CV curves in Figure 1, also an impact of annealing temperature on the minority response time is visible either induced by defects [36][37][38] or by peripheral inversion regions surrounding the metal gate pads as reported by Connor et al 39 The hystereses are remarkably low and vary in a range of 0.36 V (550 C) and <0.1 V (500 C) as depicted in Table I. If compared to the as deposited sample ( Fig.…”

Section: Resultsmentioning

confidence: 81%

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

Bethge

Zimmermann

Lutzer

et al. 2014

Journal of Applied Physics

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The impact of thermal post deposition annealing in oxygen at different temperatures on the Ge/Y2O3 interface is investigated using metal oxide semiconductor capacitors, where the yttrium oxide was grown by atomic layer deposition from tris(methylcyclopentadienyl)yttrium and H2O precursors on n-type (100)-Ge substrates. By performing in-situ X-ray photoelectron spectroscopy, the growth of GeO during the first cycles of ALD was proven and interface trap densities just below 1 × 1011 eV−1 cm−2 were achieved by oxygen annealing at high temperatures (550 °C–600 °C). The good interface quality is most likely driven by the growth of interfacial GeO2 and thermally stabilizing yttrium germanate.

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Section: Resultsmentioning

confidence: 81%

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

Bethge

Zimmermann

Lutzer

et al. 2014

Journal of Applied Physics

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“…To this date, the interface between the Ge surface and the gate dielectric remains the most important and challenging problem for Ge MOS devices. Methods in achieving low interface trap density (D it ) values for Ge gate stacks [1][2][3][4][5][6][7] include plasma oxidation, high-pressure oxidation on Ge surface. [8][9][10] These methods of using GeO x passivation have demonstrated Ge MOS field-effect transistors (MOSFETs) with high electron and hole mobility.…”

Section: Introductionmentioning

confidence: 99%

In-situ deposited HfO₂ and Y₂O₃ on epi-Si/p-Ge—a comparative study of the interfacial properties and reliability

Chu

Wan

Cheng

et al. 2022

Jpn. J. Appl. Phys.

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Single-crystal Si films six-monolayers (MLs) in thickness were epitaxially grown on Ge(001) surface to minimize the formation of undesirable GeOx with subsequent deposition of HfO2 and Y2O3. The interfacial properties and reliability of the in-situ deposited high-κ oxides on epi-Si/p-Ge(001) were compared. We have achieved interface trap density (Dit ) values of (1- 3) × 1011 eV-1 cm-2 in the Y2O3/epi-Si/p-Ge, which are two times lower than those of the HfO2/epi-Si/p-Ge(001). The capacitance-equivalent-thicknesses (CET) under different annealing conditions were extracted to analyze the interdiffusion in the gate stacks under various thermal treatments. Y2O3/epi-Si/p-Ge exhibited higher thermal stability than HfO2. In both high-κ’s gate stacks, the effective charge sheet densities (∆Neff ) are lower than the targeted value of 3 × 1010 cm-2. Compared to the Y2O3 gate stacks, attainment of a high acceleration factor of 11 in the HfO2/epi-Si/p-Ge gate stacks suggested an improved defect-carrier decoupling in the latter stacks.

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“…Usually, a decrease in deposition temperature causes the increment of D it , and the high frequency capacitance under the inversion condition can be observed in frequency dispersion for example. [22][23][24][25] In this study, we prepared MOS capacitors with ALD-GeO 2 insulator films on Ge with various deposition temperatures, and we considered the effect of GeO 2 deposition temperature on the electrical properties of the Ge gate stack focusing on the frequency dispersion in the depletion, weak inversion, and strong inversion regions.…”

Section: Introductionmentioning

confidence: 99%

Effect of GeO₂ deposition temperature in atomic layer deposition on electrical properties of Ge gate stack

Kanematsu

Shibayama

Sakashita

et al. 2016

Jpn. J. Appl. Phys.

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We investigated the effect of GeO2 deposition temperature (T depo) on electronic properties of Al/Al2O3/GeO2/Ge MOS capacitors. Capacitance–voltage characteristics show frequency dispersions under depletion and strong inversion conditions, which can be attributed from the interface states at the atomic layer deposition (ALD)-GeO2/Ge interface and from the defect states in the quasi-neutral region in the Ge substrate, respectively. We found that the interface state density (D it) shows similar values and energy distributions as T depo decreases to 200 from 300 °C, while a higher D it is observed at a T depo of 150 °C. Also, from the temperature dependence of conductance, the frequency dispersion under the strong inversion condition can be related to the minority carrier diffusion to the quasi-neutral region of the Ge substrate. The frequency dependence of conductance reveals that the undesirable increment of the bulk defect density can be suppressed by decreasing T depo. In this study, the bulk defect density in a MOS capacitor prepared at a T depo of 200 °C decreases one tenth compared with that at a T depo of 300 °C. The ALD of GeO2 at a low temperature of around 200 °C is effective for both obtaining a low D it and preventing the undesirable introduction of bulk defect density.

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Process temperature dependent high frequency capacitance-voltage response of ZrO2/GeO2/germanium capacitors

Cited by 17 publications

References 15 publications

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

In-situ deposited HfO₂ and Y₂O₃ on epi-Si/p-Ge—a comparative study of the interfacial properties and reliability

Effect of GeO₂ deposition temperature in atomic layer deposition on electrical properties of Ge gate stack

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Process temperature dependent high frequency capacitance-voltage response of ZrO2/GeO2/germanium capacitors

Cited by 17 publications

References 15 publications

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing

In-situ deposited HfO2 and Y2O3 on epi-Si/p-Ge—a comparative study of the interfacial properties and reliability

Effect of GeO2 deposition temperature in atomic layer deposition on electrical properties of Ge gate stack

Contact Info

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In-situ deposited HfO₂ and Y₂O₃ on epi-Si/p-Ge—a comparative study of the interfacial properties and reliability

Effect of GeO₂ deposition temperature in atomic layer deposition on electrical properties of Ge gate stack