Process technology scaling in an increasingly interconnect dominated world

Abstract

The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.

Nano-Structure-Controlled Very Low Resistivity Cu Wires Formed by High Purity and Optimized Additives

“…Cu wire resistivity increase due to miniaturization is a crucial and shared issue to be solved among leading LSI manufacturing companies. Researchers [1]- [3] have worked on the thinning of high resistivity barrier metals. Replacement of high resistivity barrier metals with low resistivity barrier metals like Ru has also been investigated [4].…”

First-Principles Evaluation of fcc Ruthenium for its use in Advanced Interconnects

“…Only Co has potential to offer lower grain boundary resistivity compared to fcc Ru but only in the case that the average grain size is smaller than about 5 nm. The actual resistance of interconnects, however, depends not only the average grain size for each metal at the dimension of interest but also on the volume of the conductor that is occupied by adhesion and wetting layers [39]. In Fig.…”

Progress on carbon nanotube BEOL interconnects

“…9 shows the electrical conductivity of SWCNT and MWCNT lines with different lengths and diameters, as compared to Cu lines. The conductivities are calculated using analytical models [18] [19], where the fitting parameters are calibrated against the ab-initio simulations described in Section III.A. A finitedifference approach is adopted to solve the Laplace equations for macroscopic resistance and capacitance (RC) extraction in complex interconnect structures: where ε, κ, and ψ are permittivity, conductivity, and potential, respectively.…”