Process Integration

El-Kareh, Badih; Hutter, Lou N.

doi:10.1007/978-3-030-15085-3_9

Cited by 10 publications

(8 citation statements)

References 16 publications

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“…Figures 5(c) and (d) illustrates the variation of g m and g m /I ds with respect to gate voltage and drain current respectively. It clearly shows that in the subthreshold region, g m is constant with respect to V gs or in other way g m varies linearly with drain current, but its dependence is square root in strong inversion region [28]. It is clear from figure 3(b) that the differential change in I ds for t fe = 22 nm is higher than that of at t fe = 24 nm, for the same change in V gs around 0.9 V. Therefore, at V gs = 0.9 V the transconductance is 11.25 mS and 6.25 mS for t fe equals to 22 nm and 24 nm respectively, which is shown in figure 5(c).…”

Section: Resultsmentioning

confidence: 93%

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off

Kumar

Maurya

Malvika

et al. 2023

Semicond. Sci. Technol.

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In the present work, a high-k dielectric HfO2 and Lead Zirconate Titanate (PZT) have been incorporated as a ferroelectric layer in the gate stack. The Ion/Ioff ratio obtained of the order of 1013, and the subthreshold swing 49.7 mV/dec are the most captivating findings of the device which outshines earlier findings. There is a significant improvement in the on-state current (Ion) and off-state current (Ioff). Furthermore, comparatively high value of transconductance (gm) and transconductance generation factor (gm/Id ), due to the incorporation of 20 nm PZT NC ferroelectric layer, insinuates that the device could be used in low power applications. These enticing findings of the proposed PZT GAA-NCFET nanowire could pave the way for low power devices.

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Section: Resultsmentioning

confidence: 93%

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off

Kumar

Maurya

Malvika

et al. 2023

Semicond. Sci. Technol.

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“…Interface traps originate from a lattice mismatch between SiO 2 and SiC and incomplete oxidation, including dangling bonds of Si and carbon (C), and Ccontaining defects [21,57]. A SiO 2 /Si interfacial transition layer is about 0.5-1 nm thick [58], whereas a SiC/SiO 2 interfacial transition layer is around several nanometers thick and related to oxidation and POA process [5,59,60].…”

Section: Interface Trapsmentioning

confidence: 99%

Bias temperature instability in SiC metal oxide semiconductor devices

Yang¹,

Wei²,

Wang³

2021

J. Phys. D: Appl. Phys.

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Although silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are commercially available, bias temperature instability (BTI) defined as shifts in V th in SiC MOSFET and V fb in MOS capacitor after the device is operated at a high temperature, seriously affects device reliability and limits further commercial applications. These instabilities are mainly attributed to charge trapping at and near the SiC/SiO 2 interface and mobile ions in a gate oxide. The consequences of V th instability are serious and can worsen the performance and lifetime of SiC MOS devices. In this review, the SiC/SiO 2 interface issue is introduced, and BTI occurring in current SiC MOS devices is described in detail. V th /V fb instability behavior induced by measurement and stress conditions, microscopic defects and instability mechanisms, recent measurement techniques of near-interfacial oxide traps, and BTI improvement resulting from the fabrication processes are described. BTI improvement mainly involves the control of charge trapping and movements of ions. The fabrication processes are related to oxidation and pre-and post-oxidation treatments. This review can help deepen our understanding of BTI and reduce its influence on SiC MOS devices performance.

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“…In this work, the change in Q f was disregarded during stress and the measurement periods. Thus, ΔV fb, shift can be written as [18,36] ∆V fb, shift = −…”

Section: Charge Separation Of V Fb Shift Induced By Varied Temperatur...mentioning

confidence: 99%

Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

Yang¹,

Gu²,

Yin³

et al. 2019

J. Phys. D: Appl. Phys.

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Bias temperature stresses (BTSs) are critical factors that cause severe threshold voltage (V th ) instability in silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this work, we studied the behavior of flatband voltage (V fb ) instability in 4H-SiC MOS capacitors under various BTSs from low temperature (LT) to high temperature (HT) considering the combined effects of interfacial traps and mobile ions. Results showed that nitrogen and nitrogen-hydrogen plasma passivation improved the V fb instability. The initial sweeping gate voltage determined the direction of V fb shift. BTSs from LT to HT induced different capacitance-voltage hysteresis characteristics. The V fb shift was further separated according to the contribution of the interface trapped, oxide trapped, and mobile ionic charges. At LT, the charge trapping dominated the shift behavior. The interface trap density was also extracted by another high-frequency and quasi-static method, which was the same as the separated interface trap density at 100 K, confirming the separation correctness of V fb shift. At room temperature, charge trapping and mobile ions with very weak mobility contributed to the V fb shift. At HT, mobile ions that counteracted the charge-trapping effect determined the V fb shift, although the additional traps were activated in the interface and oxide. Physical models of V fb instability under different temperature stresses were proposed. Finally, we chose the 100 K, 273 K, and 423 K to analyze gate bias stresses and stress time induced V fb instabilities as well as their mechanisms.

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Process Integration

Cited by 10 publications

References 16 publications

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off

Bias temperature instability in SiC metal oxide semiconductor devices

Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

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Process Integration

Cited by 10 publications

References 16 publications

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I on/I off

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I on/I off

Bias temperature instability in SiC metal oxide semiconductor devices

Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

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Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off

Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I _on/I _off