Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

Abstract

Bias temperature stresses (BTSs) are critical factors that cause severe threshold voltage (V th ) instability in silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this work, we studied the behavior of flatband voltage (V fb ) instability in 4H-SiC MOS capacitors under various BTSs from low temperature (LT) to high temperature (HT) considering the combined effects of interfacial traps and mobile ions. Results showed that nitrogen and nitrogen-hydrogen plasma passivation improved the V fb instability. The initial sweeping gate voltage determined the direction of V fb shift. BTSs from LT to HT induced different capacitance-voltage hysteresis characteristics. The V fb shift was further separated according to the contribution of the interface trapped, oxide trapped, and mobile ionic charges. At LT, the charge trapping dominated the shift behavior. The interface trap density was also extracted by another high-frequency and quasi-static method, which was the same as the separated interface trap density at 100 K, confirming the separation correctness of V fb shift. At room temperature, charge trapping and mobile ions with very weak mobility contributed to the V fb shift. At HT, mobile ions that counteracted the charge-trapping effect determined the V fb shift, although the additional traps were activated in the interface and oxide. Physical models of V fb instability under different temperature stresses were proposed. Finally, we chose the 100 K, 273 K, and 423 K to analyze gate bias stresses and stress time induced V fb instabilities as well as their mechanisms.

Ozone oxidation of 4H-SiC and flat-band voltage stability of SiC MOS capacitors

“…First, many interface traps and NIOTs can be occupied by electrons due to the decrease in the difference between E f and E c , resulting from the decrease in test temperature. [9,34] Second, a low temperature can reduce the de-trapping rate of trapped carriers. [9,35] Therefore, the electrical signals of many traps can be tested by C-V curves.…”

“…[9,34] Second, a low temperature can reduce the de-trapping rate of trapped carriers. [9,35] Therefore, the electrical signals of many traps can be tested by C-V curves. We observed that ∆V fb decreases with the increase in O 3 oxidation temperature, indicating that V fb BTI can be effectively improved by O 3 oxidation at high temperatures.…”

“…[35] When they conduct C-V tests at low temperatures, the mobile ions hardly move, leading to a minimal influence on ∆V mg . [9,36] Therefore, ∆V mg only has a linear relationship with the oxide trap charge at low temperatures. We extract the values of ∆V mg of the various SiC MOS capacitors for a quantitative analysis of NIOTs.…”

“…[7] The V th /flat-band voltage (V fb ) instability is mainly due to the interface trap and near interface oxide trap (NIOT) formed near the interface during traditional dry oxidation. [8][9][10] These defects can be eliminated by POA and improved oxidation processes; [5,[11][12][13] the latter can suppress the generation of these defects fundamentally by increasing the oxidant concentration near the SiC/silicon dioxide (SiO 2 ) interface. [14][15][16] Improved oxidation processes include wet oxidation, [17] NO oxidation, [6] plasma oxidation, [18,19] and ozone (O 3 ) oxidation.…”

Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer

“…As the voltage increases, the window of the curve will gradually become smaller and then turn into a normal counterclockwise hysteresis curve. This is due to the carrier injection from the top electrode into the defect state of the SiN x layer [ 30 , 31 ]. A thicker SiN x control layer can block the transfer of carriers between the top electrode and the nc-Si dots, thereby improving the carrier injection efficiency from the Si substrate to the nc-Si dots.…”