2011
DOI: 10.1109/jetcas.2011.2135530
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Process Compensation Loops for High Speed Ring Oscillators in Sub-Micron CMOS

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Cited by 9 publications
(2 citation statements)
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“…Both bandwidths are around , which is the readout clock frequency. Those bandwidths were obtained from other works [ 70 , 71 , 72 , 73 ] regarding frequency clock variations in digital circuits designed in a CMOS process with the same feature size. The best-case value comes from thermal drift variation studies [ 70 , 71 ] and the worst case, from Monte Carlo analyses [ 72 , 73 ].…”
Section: Results and Discussionmentioning
confidence: 99%
“…Both bandwidths are around , which is the readout clock frequency. Those bandwidths were obtained from other works [ 70 , 71 , 72 , 73 ] regarding frequency clock variations in digital circuits designed in a CMOS process with the same feature size. The best-case value comes from thermal drift variation studies [ 70 , 71 ] and the worst case, from Monte Carlo analyses [ 72 , 73 ].…”
Section: Results and Discussionmentioning
confidence: 99%
“…Once the PLL is started, frequency drifts caused by extreme temperature variations could push the control voltage of the VCO out of the fine-tuning range, causing the PLL to become out of lock. Although temperature-related frequency drifts can be compensated by schemes such as tuning the tail current [23,24] and adding extra compensation loops [25], these methods lead to complex designs and extra area. To compensate the temperature drift with minimum circuitry, an N-well resistor which exhibits positive TC is employed.…”
Section: Frequency Synthesizer With Temperature Compensationmentioning
confidence: 99%