A ±3.07% frequency variation clock generator implemented using HV CMOS process

Wang, Chua-Chin; Wang, Deng-Shian; Sung, Tzu-Chiao; Hsieh, Yi-Jie; Lee, Tzung-Je

doi:10.1016/j.mejo.2014.12.008

Cited by 2 publications

(1 citation statement)

References 17 publications

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“…Most of the polarization circuits and embedded digital (MOS transistors, resistors, NE555, Arduino, etc.) can develop and generate a variable number of pulses, as well as the PWM, but they still limit in surface and in Input/output [6]- [8]. The low percentage of the device logic blocks occupied by the PWM implementation on the FPGA allows the integration of multiple control operations [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Zemmouri¹,

Elgouri²,

Alareqi³

et al. 2017

IJPEDS

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This paper presents an embedded control application of clock frequency to control the pulse width of the output signals, implemented on field programmable get array. This control allows the creation of lines of Pulsewidth modulation depending on the numbers of card outputs, without using the specific "Timers /Counters" blocks; this method is effective to adjust the amount of power supplied to an electrical charge. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. Performance of these designimplemented in field programmable get array virtex 5 card, and signals displayed on an asciloscope. Keyword:EDK/SDK FPGA Vertix5 Micoblaze PWM

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Zemmouri¹,

Elgouri²,

Alareqi³

et al. 2017

IJPEDS

View full text Add to dashboard Cite

show abstract

A high-accuracy DCO with hybrid architecture

et al. 2017

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In this paper, a novel hybrid digital-controlled oscillator (DCO) is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts: DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature (PVT) variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80 °C temperature variations in TT, FF, SS corners.

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A ±3.07% frequency variation clock generator implemented using HV CMOS process

Cited by 2 publications

References 17 publications

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

A high-accuracy DCO with hybrid architecture

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