Problems Using Boundary-Scan for Memory Cluster Tests

Treuren, B.G. Van; Chiang, Chen-Huan; Honaker, Kenneth

doi:10.1109/test.2008.4700645

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2016

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“…Much prior work has been done related to memory test. Boundary scan [1] introduced DC and stuck-at tests. In [3] the authors have demonstrated a physical memory fault model to test BIST algorithms.…”

Section: Introductionmentioning

confidence: 99%

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

et al. 2016

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3D stacked integrated circuit presents unique challenges to testability due to the lack of probe points. High speed memory and IO require fast, and potentially complex link training. Further, compared to the desktop CPUs, phones and tablets present low power challenges for Intel chips. This paper presents the architecture of a reusable Built-InSelf-Test (BIST) engine called CPGC, implemented on Intel 14nm 3DS IC. It is capable of auto-repair for detected memory defects. Silicon results demonstrate CPGC enables easy debug of Inter-symbol-interference (ISI) and crosstalk issues to improve the probe-ability of 3DS IC. It also enables quick and complex IO link training of all memory and IO subsystem. Further, CPGC improved validation time by 3x, and reduced system-on-achip (SOC) and platform power by 5% to 11% through closed loop circuit power optimization/training. This reusable CPGC BIST engine IP solution has been successfully designed into at least 11 Intel CPU/SOCs.

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Section: Introductionmentioning

confidence: 99%