Probing the limits of gate-based charge sensing

Abstract

Quantum computation requires a qubit-specific measurement capability to readout the final state of individual qubits. Promising solid-state architectures use external readout electrometers but these can be replaced by a more compact readout element, an in situ gate sensor. Gate-sensing couples the qubit to a resonant circuit via a gate and probes the qubit's radiofrequency polarizability. Here we investigate the ultimate performance of such a resonant readout scheme and the noise sources that limit its operation. We find a charge sensitivity of 37 me Hz À 1/2 , the best value reported for this technique, using the example of a gate sensor strongly coupled to a double quantum dot at the corner states of a silicon nanowire transistor. We discuss the experimental factors limiting gate detection and highlight ways to optimize its sensitivity. In total, resonant gate-based readout has advantages over external electrometers both in terms of reduction of circuit elements as well as absolute charge sensitivity.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

“…We characterise one exemplary single QD and demonstrate that different DQD configurations can be set at will. Building on previous demonstrations [10][11][12] results provide a way to scale up CMOS quantum information architectures and to create reconfigurable silicon multi-dot arrangements. The device presented here is a fully depleted silicon-oninsulator (FDSOI) nanowire field-effect transistor with four independently addressable top-gates.…”

“…We characterise one exemplary single QD and demonstrate that different DQD configurations can be set at will. Building on previous demonstrations [10][11][12] silicon top-gates of length L = 40 nm are arranged around the sides of a 82 nm × 82 nm square at 45 • with respect to transport direction as shown in white dashes in the scanning electron micrograph of a similar device in Fig.1(a). Gate-to-gate distances are S G1−G2 = S G2−G3 = 30 nm, and the channel width W is 87 nm.…”

“…A further advantage of using Si is the possibility to integrate with current complementary-metaloxide-semiconductor (CMOS) technology [5-8] and leverage its established industrial platform for large scale circuits. Recently, the integration of Si quantum dots and double quantum dots (DQD) into CMOS technology has been taken a step further with reports of fewelectron QDs, DQDs, and donor-QD hybrids created within industry-standard Si nanowire transistors [9][10][11][12]. Combined with a gate-based readout scheme that alleviates the need for a separate charge sensor [10-14] these approaches pave the way towards a large scale quantum computing architecture based on current CMOS technology.…”

“…Each top-gate wraps around two faces of the intrinsic channel and is separated from the other top-gates by the Si 3 N 4 spacers and from the channel by 5 nm of SiO 2 [15]. A quantum dot can be created under each gate at the top-most corners of the channel due to the so-called corner effect [10,11,16]. Each QD is controlled by its respective gate voltage V g(x) , while a global backgate voltage V bg may be applied through the Si substrate.…”

“…It incorporates one, or a pair, of CMOS corner state quantum dots [10,11] in a variety of configurations. Each of the four gates can host an independently tunable quantum dot created in the square channel by electrostatic enhancement and confinement resulting from the topgate electrodes and accompanying silicon nitride spacers.…”