Probing Assessment Framework and Evaluation of Antiprobing Solutions

Wang, Huanyu; Shi, Qihang; Forte, Domenic; Tehranipoor, Mark

doi:10.1109/tvlsi.2019.2901449

Cited by 24 publications

(21 citation statements)

References 16 publications

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“…By fixing the dwell time to 0.1 ms and the current at 48 pA they achieved an absolute depth of 1.8 µm with a relative diameter less than 300 nm, which gives a ratio of six (R F IB = depth diameter = 6). In [17,20], the authors described a methodology allowing to analyze a hardware implementation protected by an active shield against probing attack. They showed on a protected implementation with an active shield, the optimal ratio necessary to bypass the shield, or conversely, deduce the ratio for which the shield remains effective.…”

Section: Fib For Probing Attackmentioning

confidence: 99%

Post-layout Security Evaluation Methodology Against Probing Attacks

Takarabt

Guilley

Souissi

et al. 2021

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Probing attack is considered to be one of the most powerful attack used to break the security and extract confidential information from an embedded system. This attack requires different bespoke equipment's and expertise. However, for the moment, there is no methodology to evaluate theoretically the security level of a design or circuit against this threat. It can be only realized by a real evaluation of a certified evaluation laboratory. For the design house, this evaluation can be expensive in term of time and money. In this paper, we introduce an innovative methodology that can be applied to evaluate the probing attack on any design at simulation level. Our method helps to extract the sensitive signals of a design, emulate different Focused Ions Beam technologies used for probing attacks, and evaluate the accessibility level of each signal. It can be used to evaluate precisely any probing attack on the target design at simulation level, hence reducing the cost and time to market of the design. This methodology can be applied for both ASIC and FPGA technology. A use-case on an AES-128 shows the efficiency of our methodology. It also helps to evaluate the efficiency of the active shield used as a countermeasure against probing attack.

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Section: Fib For Probing Attackmentioning

confidence: 99%

Post-layout Security Evaluation Methodology Against Probing Attacks

Takarabt

Guilley

Souissi

et al. 2021

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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“…An extremely sensitive local charge sensor is placed close to the chip surface, which could capture the charge changes and store the state for later Fig. 13: Working principle of active shield and bypass attack on active shield [33]. Fig.…”

Section: Defense Against Contact-based Probing Attacksmentioning

confidence: 99%

“…(a) FIB deposits Platinum in the milling cavity to build a conducting path (green) from the target wire; (b) The deposited conducting path serves as a electrical pad for the probe contact[33].…”

mentioning

confidence: 99%

Defense-in-depth: A recipe for logic locking to prevail

Rahman

Wang

et al. 2020

Integration

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Logic locking has emerged as a promising solution for protecting the semiconductor intellectual Property (IP) from the untrusted entities in the design and fabrication process. Logic locking hides the functionality of the IP by embedding additional key-gates in the circuit. The correct output of the chip is produced, once the correct key value is available at the input of the key-gates. The confidentiality of the key is imperative for the security of the locked IP as it stands as the lone barrier against IP infringement. Therefore, the logic locking is considered as a broken scheme once the key value is exposed. The research community has shown the vulnerability of the logic locking techniques against different classes of attacks, such as Oracle-guided and physical attacks. Although several countermeasures have already been proposed against such attacks, none of them is simultaneously impeccable against Oracle-guided, Oracle-less, and physical attacks. Under such circumstances, a defense-in-depth approach can be considered as a practical approach in addressing the vulnerabilities of logic locking. Defense-in-depth is a multilayer defense approach where several independent countermeasures are implemented in the device to provide aggregated protection against different attack vectors. Introducing such a multilayer defense model in logic locking is the major contribution of this paper. With regard to this, we first identify the core components of logic locking schemes, which need to be protected. Afterwards, we categorize the vulnerabilities of core components according to potential threats for the locking key in logic locking schemes. Furthermore, we propose several defense layers and countermeasures to protect the device from those vulnerabilities. Finally, we turn our focus to open research questions and conclude with suggestions for future research directions.

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“…Countermeasures seek to prevent and/or detect the physical access. Solutions include, e.g., shielding structures in the BEOL [29][30][31], deflection or scrambling structures in the substrate [32], and detector circuitry [33]. Earlier studies such as [34] also considered formally secure techniques.…”

Section: Physical Read-out and Probingmentioning

confidence: 99%

Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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Probing Assessment Framework and Evaluation of Antiprobing Solutions

Cited by 24 publications

References 16 publications

Post-layout Security Evaluation Methodology Against Probing Attacks

Post-layout Security Evaluation Methodology Against Probing Attacks

Defense-in-depth: A recipe for logic locking to prevail

Hardware Security For and Beyond CMOS Technology

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