Probability models for pseudorandom test sequences

McCluskey, E.J.; Makar, S.; Mourad, S.; Wagner, K.D.

doi:10.1109/43.3131

Cited by 63 publications

(9 citation statements)

References 10 publications

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“…The aliasing probability in parallel signature analysis is studied in the following context: 1) Test stimulus is derived from random pattern generators. Although in reality only pseudorandom pattern generators are used; their characteristics can be approximately modeled by the characteristics of a random pattern generator [11]. 2) The circuit under test is combinational.…”

Section: Signature Analysis and Aliasingmentioning

confidence: 99%

“…The Bernoulli error model has been widely used by several researchers, [5], [8], [10], [11], [14], [15], [16], [18], [19], [24]. In the Bernoulli error model, output errors are assumed to occur with probability p, called the detection probability [11], in the presence of a fault. An output error for a particular fault is an event where the output of the faulty circuit is different from the output of the fault free circuit.…”

Section: Error Models Aliasing Probability and Previous Researchmentioning

confidence: 99%

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Parallel signature analysis design with bounds on aliasing

Saxena

McCluskey

1997

IEEE Trans. Comput.

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This paper presents parallel signature design techniques that guarantee the aliasing probability to be less than 2/L, where L is the test length. Using y signature samples, a parallel signature analysis design is proposed that guarantees the aliasing probability to be less than (y/L) y/2 . Inaccuracies and incompleteness in previously published bounds on the aliasing probability are discussed. Simple bounds on the aliasing probability are derived for parallel signature designs using primitive polynomials.

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Section: Signature Analysis and Aliasingmentioning

confidence: 99%

Section: Error Models Aliasing Probability and Previous Researchmentioning

confidence: 99%

Parallel signature analysis design with bounds on aliasing

Saxena

McCluskey

1997

IEEE Trans. Comput.

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“…Probabilistic treatment of testing problems in combinational circuits has been utilized by many authors in areas such as signal probability calculation, random pattern testability estimation, fault grading, and guidance to test generation [1,2,3,4,14,15,16,17,18,21,23,24,25,30,31,32,35]. The use of Shannon's expansion theorem jointly with the cutting algorithm to achieve tighter bounds on signal probability was proposed in [30].…”

Section: ) Bist With Pseudorandom Input Patterns and Output Compactimentioning

confidence: 99%

Combined probabilistic testability calculation and compact test generation for PLAs

Reppen

Einar

1991

J Electron Test

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PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved. 1

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“…The test patterns generated by an LFSR have a guaranteed pseudorandom property that can be used to reliably predict fault coverage given the detection probabilities of the faults in the circuit [10]. This is not the case for the test patterns that are generated during circular BIST.…”

Section: Introductionmentioning

confidence: 99%

Circular BIST with state skipping

Touba

2002

IEEE Trans. VLSI Syst.

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Abstract-Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.Index Terms-Built-in self-test (BIST), built-in testing, circuit testing, design for testability, limit cycles, pseudorandom pattern generation, scan chains.

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Probability models for pseudorandom test sequences

Cited by 63 publications

References 10 publications

Parallel signature analysis design with bounds on aliasing

Parallel signature analysis design with bounds on aliasing

Combined probabilistic testability calculation and compact test generation for PLAs

Circular BIST with state skipping

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