Probability calculation of read failures in nano-scaled SRAM cells under process variations

Abstract

Abstract-In this paper, we present an accurate method for predicting the read failure probability of SRAM cells. First, using a simple I-V model for transistors, analytical expressions for the V read and V trip of SRAM cells are obtained. These expressions are subsequently used to derive a fairly accurate model for the read margin of SRAM cells. Then, using Jacobian determinant, the joint probability density function for the V read and V trip is calculated without assuming any specific distribution function for its probability. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations for a 32 nm CMOS technology. The study shows that the proposed technique has on average about 31% lower error when compared to the previous approach. In addition to a higher accuracy, the method has the advantage of not being restricted to a specific probability distribution form.

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

“…In [32], the authors report on optimizing the energy-delay product in flip-flops affected by NBTI aging. In [4], a work is reported on estimating the probability of read failure induced by process variations in SRAM cells. A preliminary subset of results of the proposed work has been presented in [35].…”

“…The voltage shift ∆ can also be seen as the minimum needed noise margin in given application [4]. In fact, the probability that a register stores a wrong bit is the probability that the voltage noise margin is smaller than the input voltage shift ∆ , i.e.…”

“…While the effects of such issues on performance figures like leakage power and delay modeling have been profoundly inquired [1][2] [16] [18], their influence on the reliability of digital designs over the years is being modelled and quantified [4][11] [13] [12] and there is a general correspondence that reliability be a key topic of future digital integrated circuits [14].…”

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

“…As subthreshold operating region is utilized for low power SRAM design, a conventional stability model is proposed for 8T cell by considering process variations but this is limited to 8T SRAM cell only [10]. Aghababa et al [11] proposed an accurate analytical model for the read margin. There are also some efforts which present modeling techniques to estimate the read failure probability of SRAM.…”

Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method

“…Recently, several analytical and semi-analytical approaches have been proposed, and they have made progress via modeling SRAM cell behavior in presence of the process variation [4][5][6][7]. In [7], the simple I-V model for transistors is used to derive a fairly accurate model for read margin of SRAM cells.…”