Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults

Schvittz, Rafael B.; Franco, Denis Teixeira; Rosa, Leomar S. da; Butzen, Paulo F.

doi:10.1109/icecs.2018.8617918

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…The SET characterization of logic gates presents an input dependence due to the different interplay relation of sensitive collecting drain areas and restoring current as shown in [32,35]. The signal switching activity is used to estimate power consumption in the design process of VLSI circuits, but it can also be used to support reliability analysis as shown in [46][47][48]. Until now, the SET cross-section calculation on this work has considered the arithmetic mean between the cross-section obtained for each input signal combination separately, i.e., the same probability to each input combination is considered.…”

Section: Impact Of Signal Probability and Input Dependencementioning

confidence: 99%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

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Section: Impact Of Signal Probability and Input Dependencementioning

confidence: 99%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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“…The reliability concept of a circuit is related to the probability of this circuit to perform the function to which it was designed, under certain conditions during a given time interval [26]. The results for error probability (EP) in [8] indicate that the equal EP values of logic gates traditionally used in reliability evaluation underestimate the real logic gates EPs, and consequently the circuit reliability. This chapter presents a method able to evaluate Single Event Transient fault susceptibility in a logic gate.…”

Section: Set Susceptibility Analysismentioning

confidence: 99%

“…The previous work was extended providing a more detailed evaluation of stick diagram level and also a electrical validation of the results. The method proposed in [8], which evaluates logic gates at transistor-level, does not evaluate precisely when parallel transistors association results in two or more nodes in layout level. Also, it is known that a logic cell can be designed in different ways, then the need for a stick level analysis is highlighted.…”

Section: Set Susceptibility Analysismentioning

confidence: 99%

“…It is known that the limitation of these methods is the simplification of the assumption of the same error probability values for all logic gates. The work proposed in [8] shows a method in transistor-level to create the logic gate probabilistic matrices. The matrices created shown that it is essential to observe the transistor arrangements to produce more accurate matrices for the logic gates that feed the probabilistic methods.…”

Section: Introductionmentioning

confidence: 99%

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An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults

Schvittz¹,

Franco²,

Rosa³

et al. 2020

IFIP Advances in Information and Communication Technology

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Technology scaling increases the integrated circuits susceptibility to Single Event Effects. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. There are several estimation methods, as Probabilistic Transfer Matrix, Signal Probability Reliability, and SPR Multi-Pass, to evaluate circuit reliability. Theses methods use probabilistic transfer matrices (PTM) of the logic gates as the starting point. Few works explore the accurate generation of these matrices. This chapter briefly reviews the reliability concepts and some circuit estimation methods that explore PTM concept and presents a method to provide gate susceptibility matrices considering faults in the stick diagram level. The proposed method enriches the logic gates probabilistic matrices creation taking into account the characteristics of the logic gates to evaluate gate reliability more precisely. The results present the importance of the proposed approach. They are shown in the mean and standard deviation of the susceptibility calculated. In terms of standard deviation, high values indicate that the cell is highly sensitive to pin assignment. A good pin assignment alternative can result in 40% reduction in susceptibility for the same logic function.

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Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients

Schvittz¹,

Butzen

Rosa

2020

2020 IEEE International Test Conference (ITC)

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Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults

Cited by 5 publications

References 14 publications

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults

Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients

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