Probabilistic Error Modeling for Two-part Segmented Approximate Adders

Celia, D.; Vasudevan, V.; Chandrachoodan, Nitin

doi:10.1109/iscas.2018.8351273

Cited by 10 publications

(4 citation statements)

References 17 publications

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“…An exception to this method for deriving error models is ETA-I [6], where the lower part sum cannot be written as a truth table. Its error metrics are derived in our earlier work [16].…”

Section: Parameterized Error Models For Low Power Approximate Addersmentioning

confidence: 99%

Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders

Dharmaraj,

Vasudevan,

Chandrachoodan

2020

Preprint

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Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits.To overcome this problem, we derive parameterized error models that can be used within any optimization framework in order to optimize the number of approximate bits. We also show that in order to accurately compute the MSE, the optimization framework needs to take into account not just the functionality of the adder, but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. We demonstrate a significant improvement of accuracy in the prediction of the noise power of DSP systems containing approximate adders.

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“…An exception to this method for deriving error models is ETA-I [6], where the lower part sum cannot be written as a truth table. Its error metrics are derived in our earlier work [16].…”

Section: Parameterized Error Models For Low Power Approximate Addersmentioning

confidence: 99%

Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders

Dharmaraj,

Vasudevan,

Chandrachoodan

2020

Preprint

Self Cite

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“…ETA-II, ETA-IIM [18], and carry skip approximate adders [10,19] are based on segmentation that truncates carry propagation. Further, the probabilistic error analysis of these segment-based adders is presented in [20,21]. To increase the applicability of approximate designs, various accuracy configurable architectures are also presented, which are reviewed in the next subsection.…”

Section: Approximate Adder Architecturesmentioning

confidence: 99%

A power and area efficient approximate carry skip adder for error resilient applications

Patel¹,

Garg²,

Kumar³

2020

Turk J Elec Eng & Comp Sci

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The compute-intensive multimedia applications on portable devices require power and area efficient arithmetic units. The adder is a prime building block of these arithmetic units and limits the overall performance. Therefore, this paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations. Further, a new power and area efficient approximate carry skip (PAEA-CSK) adder is proposed using the novel adder segment. The effectiveness of the proposed PAEA-CSK adder is evaluated and compared over the existing adders by implementing them in VHDL and synthesizing using the Synopsys Design Compiler with the 65nm TSMC CMOS Library. The synthesis result shows that the proposed PAEA-CSK adder requires 27.28% and 18.03% less area and power, respectively, over the existing carry skip-based approximate adder with the same accuracy. Further, the Sobel edge detector (SED) embedded with the proposed adder improves PSNR by a minimum of 16.94 dB over the SED embedded with a nonzeroing bit-truncation adder.

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“…The experimental results applied the methodology on state-of-the-art multipliers to compute their probability mass functions and predicted their performance in an image-processing application. The authors of [21] proposed a probabilistic analysis methodology for analyzing two-part segmented adders and derived the mean error distance and mean square error in the approximate adders.…”

Section: Related Workmentioning

confidence: 99%

Error metrics determination in functionally approximated circuits using SAT solvers

2020

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Approximate computing is an emerging design paradigm that offers trade-offs between output accuracy and computation efforts by exploiting some applications' intrinsic error resiliency. Computation of error metrics is of paramount importance in approximate circuits to measure the degree of approximation. Most of the existing techniques for evaluating error metrics apply simulations which may not be effective for evaluation of large complex designs because of an immense increase in simulation runtime and a decrease in accuracy. To address these deficiencies, we present a novel methodology that employs SAT (Boolean satisfiability) solvers for fast and accurate determination of error metrics specifically for the calculation of an average-case error and the maximum error rate in functionally approximated circuits. The proposed approach identifies the set of all errors producing assignments to gauge the quality of approximate circuits for real-life applications. Additionally, the proposed approach provides a test generation method to facilitate design choices, and acts as an important guide to debug the approximate circuits to discover and locate the errors. The effectiveness of the approach is demonstrated by evaluating the error metrics of several benchmark-approximated adders of different sizes. Experimental results on benchmark circuits show that the proposed SAT-based methodology accurately determines the maximum error rate and an average-case error within acceptable CPU execution time in one go, and further provides a log of error-generating input assignments. OPEN ACCESSCitation: Abed S, Behiry AAMR, Ahmad I (2020) Error metrics determination in functionally approximated circuits using SAT solvers. PLoS ONE 15(1): e0227745. https://doi.org/10.

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Probabilistic Error Modeling for Two-part Segmented Approximate Adders

Cited by 10 publications

References 17 publications

Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders

Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders

A power and area efficient approximate carry skip adder for error resilient applications

Error metrics determination in functionally approximated circuits using SAT solvers

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