Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis

Sengupta, Anirban; Sedaghat, Reza; Sarkar, Pallabi; Sehgal, Summit

doi:10.1109/ccece.2011.6030509

Cited by 2 publications

(3 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is a combination of the priority factor method and fuzzy search technique that is rapid and accurate, used in the evaluation and selection in the architecture design space. Other hybrid approaches that use an aggregation method are presented in [44], which is a combination of a priority factor-based heuristic and a dependency matrix algorithm. is iterative heuristic method has a considerably good exploration runtime while delay and area are used as the objective functions.…”

Section: Problem-specific Heuristic Approachesmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

View full text Add to dashboard Cite

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

show abstract

Section: Problem-specific Heuristic Approachesmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

View full text Add to dashboard Cite

show abstract

“… Another developed approach focused on reducing the static power consumption of designs under the expenditure of minimum control steps. For this purpose, a heuristic was developed which is based on a priority indicator and the depency matrix algorithm (Sengupta et al, 2011).…”

Section: Previous Workmentioning

confidence: 99%

“…Most of the techniques optimized power consumption while having negative effects on the delay or area. Previous multi-voltage techniques which aimed to optimize power consumption did not account for voltage conversions and they also targeted low synthesis levels, such as floorplanning or even transistor level layouts (Ahuja et al, 2009;Costa, Bampi, & Monteiro, 2001;Goel & Singh, 2012;Mohanty, Ranganathan, Kougianos, & Patra, 2008;Sengupta, Sedaghat, Sarkar, & Sehgal, 2011;Wei, Li, & Zhang, 2010;Wu, Xu, Yu, Zheng, & Bian, 2009;Wu, Xu, Zheng, & Mao, 2010). This work proposes novel approaches which can solve the above problems and yield better results.…”

Section: Introductionmentioning

confidence: 99%

Parallel multi-voltage power minimization in VLSI circuits. (c2013)

Younes¹

View full text Add to dashboard Cite

Power consumption minimization is nowadays considered a main challenge to VLSI designers, especially with the growth of the mobile computing industry. Previous studies have tried minimizing power consumption at the expense of the overall circuit delay, and have mostly focused at optimizing power at the lower levels of abstractionduring placement and routing. This work presents novel techniques to minimize power consumption during behavioral synthesis and to reduce execution runtime through parallel processing. Design space exploration at higher levels of abstraction yields greater optimization in power, area, and delay; thus, the first contribution intelligently reduces voltages of non-critical paths in order to decrease total power consumption at the behavioral level. Voltage reductions are performed while minimizing the number of voltage conversions introduced in the circuit and maintaining the critical path delay. The second contribution concentrates on exploiting parallelism by distributing independent synthesis tasks to different processing units in the goal of reducing solution exploration time. A synthesis software suite was implemented to test the proposed approaches. Power consumption was reduced considerably with a negligible overhead of voltage conversion modules. Furthermore, design space exploration time declined significantly due to the use of parallel programming.

show abstract

Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis

Cited by 2 publications

References 6 publications

Development of Multiobjective High-Level Synthesis for FPGAs

Development of Multiobjective High-Level Synthesis for FPGAs

Parallel multi-voltage power minimization in VLSI circuits. (c2013)

Contact Info

Product

Resources

About