Prediction router: Yet another low latency on-chip router architecture

Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu; Yoshinaga, Tsutomu

doi:10.1109/hpca.2009.4798274

Cited by 78 publications

(64 citation statements)

References 18 publications

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“…By assuming an average link utilization of 50% for the 64 nodes torus of 800Gbps data transmission bandwidth, we estimated the energy consumed by the two networks. When using the prediction router the energy consumed is majorated by an extra 9% of the electrical network energy due to the extra overhead added by the prediction router [6]. Fig.…”

Section: Power Consumption Estimationmentioning

confidence: 99%

“…3) And a kill signal is added at each output channel in order to remove miss-routed flits when the prediction fails [6]. The predictor in an input-channel forecasts which output channel will be used by the next packet transfer before it reaches the input-channel.…”

Section: Predictive Switching Based Path Setupmentioning

confidence: 99%

“…In this paper, we propose predictive switching [6] and a reservation based path setup techniques for the electrical control network to reduce the setup latency of a HPNoC. Since the circuit setup latency plays a key role in the overall performance of HPNoC [11], we use these techniques to reduce the path setup latency.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Adi

Matsutani

Koibuchi

et al. 2011

IJNC

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Electrical network-on-chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Re- 244International Journal of Networking and Computing cent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and an electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC). In this paper, we propose a predictive switching and a reservation based path setup techniques to reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By using these techniques, it is possible to reduce the latency for end-to-end communication in a HPNoC improving its overall performance. In the simulation, we use a cycle accurate simulator under uniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The results show that the proposed techniques considerably improve the overall latency of HPNoC.

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Section: Power Consumption Estimationmentioning

confidence: 99%

Section: Predictive Switching Based Path Setupmentioning

confidence: 99%

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An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Adi

Matsutani

Koibuchi

et al. 2011

IJNC

Self Cite

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“…Also, the advances in NoC technology now result in considerably complex designs. For example, router pipelines have evolved from a simple stage-by-stage organization to a set of prediction and speculation techniques to reduce the latency of packets [11,13,14]. Regarding routing algorithms, while XY routing for mesh topology is often used for its simplicity, many other kinds of routing algorithms exist for various purposes.…”

Section: Related Workmentioning

confidence: 99%

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

Han

Lee

Choi

2014

Proceedings of the 2014 International Workshop on Network on Chip Architectures

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Tree-Mesh Heterogeneous Topology forLow-Latency NoC SUNGJU HAN DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING COLLEGE OF ENGINEERING SEOUL NATIONAL UNIVERSITYIn Network-on-Chip (NoC), topology is one of the most important design choices that determine performance and power consumption. Mesh, being the most popular NoC topology for many researches and products, is mainly tailored towards high throughput. However, many researches show that NoCs rarely operate under heavy load and that latency is often much more critical in practice. In this paper, I show that by adding a small tree network to assist the baseline mesh network, the zero-load latency can be greatly reduced while still maintaining the high throughput. For the management of the hybrid network, I propose a novel algorithm to steer each packet to different networks based on hop-count gain. The algorithm also includes latency ii monitoring scheme and contention monitoring scheme in order to prevent tree network to get contested too much. Experiments were performed not only on synthetic traffics but also on real application workloads to evaluate the performance of the proposed design. The results show improvements on zero-load latency, throughput, and moreover, energy consumption.

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“…Single-cycle router pipelines have been proposed in the past [24,25,31] for unicast flits. In these designs, the router pipeline on the critical path reduces to just Switch Traversal (ST).…”

Section: Introductionmentioning

confidence: 99%

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

Krishna

Peh

Beckmann

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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The prevalence of multicore architectures has accentuated the need for scalable cache coherence solutions. Many of the proposed designs use a mix of 1-to-1, 1-to-many (1-to-M), and many-to-1 (M-to-1) communication to maintain data coherence and consistency. The on-chip network is the communication backbone that needs to handle all these flows efficiently to allow these protocols to scale. However, most research in on-chip networks has focused on optimizing only 1-to-1 traffic. There has been some recent work addressing 1-to-M traffic by proposing the forking of multicast packets within the network at routers, but these techniques incur high packet delays and power penalties. There has been little research in addressing M-to-1 traffic.We propose two in-network techniques, Flow Across Network Over Uncongested Trees (FANOUT) and Flow AggregatioN In-Network (FANIN), which perform efficient 1-to-M forking and M-to-1 aggregation, respectively, such that packets incur only single-cycle delays at most routers along their path, thus approaching an ideal network (one that incurs only wire delay/energy). Full-system simulations on a 64-core CMP with SPLASH-2 and PARSEC benchmarks show that FANOUT and FANIN together reduce runtime by 14.9% and network energy by 40.2%, on average, compared to state-of-the-art networks, operating at just 1% and 9.6% above the runtime and energy of an ideal network.

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Prediction router: Yet another low latency on-chip router architecture

Cited by 78 publications

References 18 publications

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

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