Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown

Lee, Yung-Huei; Mielke, N.; Agostinelli, M.; Gupta, Sarthak; Lu, Ryan; McMahon, W.

doi:10.1109/relphy.2006.251187

Cited by 45 publications

(26 citation statements)

References 22 publications

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“…The idea is based on the weakestlink assumption, that the failure of any individual device will cause the failure of the whole chip. Recently, new approaches have been proposed to improve the prediction accuracy by empirical calibration using real circuit test data [124], or by considering the variation of gate-oxide thickness [125]. The former is empirical and hard to generalize, while the latter does not consider the effect of breakdown location.…”

Section: B Gate Oxide Breakdownmentioning

confidence: 99%

Overcoming Variations in Nanometer-Scale Technologies

Sapatnekar

2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and enviromental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.

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Section: B Gate Oxide Breakdownmentioning

confidence: 99%

Overcoming Variations in Nanometer-Scale Technologies

Sapatnekar

2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…Oxide-breakdown-induced logic failure is a weakest-link problem, because failure of any individual logic cell causes the failure of the entire circuit 6 . Prior approaches did not adequately differentiate between breakdown events that cause failure and those that do not.…”

Section: Circuit-level Failure Analysismentioning

confidence: 99%

“…6 Some such failures may lie on false paths and be masked out, but we make the reasonable assumption that the probability that a cell lies on a false path is low, and can be neglected.…”

Section: Theorem 1 the Probability Distribution W(t) Of The Time Tomentioning

confidence: 99%

“…The idea is based on the weakest-link assumption, that the failure of any individual device will cause the failure of the whole chip. Recently, new approaches have been proposed to improve the prediction accuracy by empirical calibration using real circuit test data [6], or by considering the variation of gate-oxide thickness [7]. The former is empirical and hard to generalize, while the latter does not consider the effect of breakdown location.…”

Section: Introductionmentioning

confidence: 99%

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Scalable methods for the analysis and optimization of gate oxide breakdown

Fang

Sapatnekar

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11× relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.

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“…[1][2][3] With nearly 30+ years of continual CMOS scaling, existing CMOS materials have now been pushed to their physical and reliability limits. Presently, at the 65nm node, gate oxide thickness is ~ 1.2nm [4] and with a leakage of ~ 100 a/cm 2 at 1.0V [5]. Interconnect low-k dielectric minimum spacing can be 70-80nm, similar to gate oxide thicknesses ~ 20 years ago; however, these low-k dielectrics are far from the quality of gate oxides in terms of electrical [6] and mechanical strength [7].…”

Section: Introductionmentioning

confidence: 99%

Reliability challenges for 45nm and beyond

McPherson¹

2006

2006 43rd ACM/IEEE Design Automation Conference

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Scaling, for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits. This will require that designers will have to be very careful with: high current densities, voltage overshoots, localized hot spots on the chip, high duty-cycle applications, and high thermalresistance packaging.In addition to the reliability issues, interconnect RC time-delay will worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects.Also, the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.

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Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown

Cited by 45 publications

References 22 publications

Overcoming Variations in Nanometer-Scale Technologies

Overcoming Variations in Nanometer-Scale Technologies

Scalable methods for the analysis and optimization of gate oxide breakdown

Reliability challenges for 45nm and beyond

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