Prediction of Alpha Particle Effect on 5-nm Vertical Field-Effect Transistors

Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node

“…Figure 5b shows electron velocity (e-velocity) and an electric-field (E-field) variations inside the NS-TFET according to particle energy. As the particle energy increased, both the e-velocity and E-field decreased, which is different from the vertical-FET (V-FET) result [25]. In V-FET, the higher particle energy increases both values.…”

“…It can be observed in Figure 6 that the peak drain current caused by the alpha particles increased when the ambient temperature increased. This result is the opposite of a previous work regarding FinFET and V-FET [25]. To analyze the results, we plotted electron mobility (e-mobility) and Shockley-Read-Hall (SRH) recombination according to ambient temperature, as shown in Figures 7 and 8, respectively.…”

“…Therefore, it can be concluded that EHPs generated by high particle energy cannot contribute to drain current fluctuations because EHPs generated by particles recombine before reaching the drain region. Drain current fluctuations are affected by electric field and carrier velocity fluctuations in addition to the EHP density generated by alpha particles [25]. Figure 5b shows electron velocity (e-velocity) and an electric-field (E-field) variations inside the NS-TFET according to particle energy.…”

“…In addition to a non-local tunneling model and alpha particle incidence dimension, the current-voltage measured data of fabricated 14-nm bulk FinFET was used to calibrate the TCAD model. First, the 3D structure of the mobility degradation was plotted using a Lombardi method along with a thin-layer mobility model, as outlined in a previous work [25]. Next, the calibrated model parameters were applied to our TCAD simulation for the 3-nm NS-TFET.…”

“…The effect of particle radiation on NS-TFET was significantly different from that of other conventional DD-FETs, and an analysis of the results was carried out. These results suggest that the NS-TFET requires a completely different design approach for optimizing the drain area in order to be less affected by radiation when designing an integrated circuit using the conventional DD-FET [25][26][27]. Figure 1 shows the 3D structure of a 3-nm node NS-TFET in Synopsys Sentaurus TCAD software (Synopsys, Mountain View, CA, USA) that was used to simulate an NS-TFET providing model incidents on a silicon semiconductor [28].…”