2004
DOI: 10.1007/978-3-540-30113-4_7
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Predictable Embedded Multiprocessor System Design

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Cited by 41 publications
(37 citation statements)
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“…Each processing tile consists of a processor, a small local memory, a local arbiter and a communication assist (CA) that is similar to the one described in [5]. A networkinterface (NI) is used to connect each tile to the network.…”
Section: Propertymentioning
confidence: 99%
“…Each processing tile consists of a processor, a small local memory, a local arbiter and a communication assist (CA) that is similar to the one described in [5]. A networkinterface (NI) is used to connect each tile to the network.…”
Section: Propertymentioning
confidence: 99%
“…The jobs are modelled as Multirate Data Flow (MRDF) graphs [3,13,20]. An MRDF graph is a directed graph ¥ § ¦ ©…”
Section: Applicationmentioning
confidence: 99%
“…We call this interval of time the relative deadline of the task. Through analysis techniques [3,17,8,19], it is possible for a given MRDF graph, annotated with worst-case execution times for all actors, and expanded with channel models [19] and a given required minimum throughput to compute feasible relative deadlines for each task to chose relative deadlines for the tasks and compute minimal buffer sizes [8]. Budget determination falls outside of the scope of this paper.…”
Section: Applicationmentioning
confidence: 99%
“…Multiprocessor systems-on-chip, like Daytona [1], Eclipse [26], Hijdra [2], and StepNP [22], use the tile-based multiprocessor template described by Culler [4]. Each tile contains one or a few processor cores and local memories.…”
Section: Architecture Platformmentioning
confidence: 99%