Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication

Stuijk, Sander; Basten, Twan; Geilen, Marc; Ghamarian, Amir Hossein; Theelen, B.D.

doi:10.1109/dsd.2006.81

Cited by 17 publications

(15 citation statements)

References 29 publications

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“…While the authors announce the resource utilization improvement of BAA, the algorithm complexity is not discussed which might have the expensive hardware implementation. A good compromise in the allocation of routes and TDMA slots for on-chip streaming communication is found by heuristic strategies in [12]. Leung et.…”

Section: Related Workmentioning

confidence: 99%

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin

Dou

2010

2010 IEEE International Conference on Computer Design

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Strict Priority Queueing (SPQ) and Weighted Round Robin (WRR) are two common scheduling techniques to achieve Quality-ofService (QoS) while using shared resources. Based on network calculus, we build analytical models for traffic flows under SPQ and WRR scheduling in on-chip wormhole networks. With these models, we can derive per-flow end-to-end delay bound. We compare the service behavior and show that WRR is not only more fair but also more flexible for QoS provision. To exhibit the potential and flexibility enabled by WRR, we develop a weight allocation algorithm to automatically assign proper weights for individual flows to satisfy their delay constraints. In particular, the weights are assigned in a way not more than necessary, in other words, to approach flows' delay constraints in order to leave room for other flows. Our experimental results validate our analysis technique and algorithms.

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Section: Related Workmentioning

confidence: 99%

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin

Dou

2010

2010 IEEE International Conference on Computer Design

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“…Each user-case entails a specific traffic pattern on NoC. This application specific nature, as opposed to the largely random traffic in chip multiprocessors, allows guaranteed service to be obtained by reserving resources at design-time [1][2][3][4][5][6]. The resources include both physical ones -links along a packet routing path, and temporal ones -time slots at each link, i.e., the resource allocation is based on Time Division Multiplexing (TDM).…”

Section: Introductionmentioning

confidence: 99%

Algorithms for power-efficient QoS in application specific NoCs

Yang

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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Quality-of-Service (QoS) is a fundamental part of Networkson-Chip (NoC) design. In application specific NoCs, guaranteed QoS is often obtained by static bandwidth reservation at design-time. The bandwidth allocation inevitably affects power-efficiency, which is crucial yet largely neglected in prior NoC QoS methods. In this work, we develop two algorithmic techniques that concurrently address power-efficiency and QoS. One is path-based integer linear programming (ILP) and the other is a negotiation-based heuristic. Both techniques support multiple user-cases. Simulation results show that our techniques significantly outperform an iterative greedy heuristic and are order of magnitude faster than conventional edge-based ILP.

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“…For example, several works have presented approaches to dynamically manage and reduce the network's power consumption [Jafri et al 2012;Mishra et al 2010;Kim et al 2011]. Others have proposed alternative scheduling [Stuijk et al 2006], resource reservation methods , and arbitration schemes that achieve better QoS or provide QoS bounds for certain types of traffic [Al Faruque et al 2006]. Several works have also described changes in network topology [Das et al 2009] and features in order to better meet the demands of applications running on the CMP [Krishna et al 2011].…”

Section: Related Workmentioning

confidence: 99%

Post-silicon platform for the functional diagnosis and debug of networks-on-chip

Abdel-Khalek

Bertacco

2014

ACM Trans. Embed. Comput. Syst.

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The increasing number of units in today's systems-on-chip and multicore processors has led to complex intrachip communication solutions. Specifically, Networks-on-Chip (NoCs) have emerged as a favorable fabric to provide high bandwidth and low latency in connecting many units in a same chip. To achieve these goals, the NoC often includes complex components and advanced features, leading to the development of large and highly complex interconnect subsystems. One of the biggest challenges in these designs is to ensure the correct functionality of this communication infrastructure. To support this goal, an increasing fraction of the validation effort has shifted to post-silicon validation, because it permits exercising network activities that are too complex to be validated in pre-silicon. However, post-silicon validation is hindered by the lack of observability of the network's internal operations and thus, diagnosing functional errors during this phase is very difficult.In this work, we propose a post-silicon validation platform that improves observability of network operations by taking periodic snapshots of the traffic traversing the network. Each node's local cache is configured to temporarily store the snapshot logs in a designated area reserved for post-silicon validation and relinquished after product release. Each snapshot log is analyzed locally by a software algorithm running on its corresponding core, in order to detect functional errors. Upon error detection, all snapshot logs are aggregated at a central location to extract additional debug data, including an overview of network traffic surrounding the error event, as well as a partial reconstruction of the routes followed by packets in flight at the time. In our experiments, we found that this approach allows us to detect several types of functional errors, as well as observe, on average, over 50% of the network's traffic and reconstruct at least half of each of their routes through the network.

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Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication

Cited by 17 publications

References 29 publications

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin

Algorithms for power-efficient QoS in application specific NoCs

Post-silicon platform for the functional diagnosis and debug of networks-on-chip

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