Precomputation-based sequential logic optimization for low power

Abstract

In this thesis, we address the problem of optimizing sequential logic circuits for low power. We present a powerful optimization method that selectively precomputes the outputs of the circuit one clock cycle before they are required and uses the precomputed values to reduce switching activity in the next clock cycle. We present different precomputation architectures that exploit this observation.The primary optimization step is the synthesis of the precomputation logic, which computes the output values of the circuit for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and, thus, has substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit.Given a sequential logic circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximum reductions in power dissipation. We present experimental results on various sequential circuits. Up to 60 percent reductions in power dissipation are possible with marginal increases in circuit area and delay.

Value-based clock gating and operation packing

“…Guarded evaluation seeks to dynamically detect which parts of a logic circuit are being used and which are not [Tiwari et al 1998a]. Logic precomputation seeks to derive a precomputation circuit that under special conditions does the computation for the remainder of the circuit [Alidina et al 1994]. Both of these techniques are analogous to conditional clocking, which can be used at the architectural level to reduce power by disabling unused units.…”

Testability Analysis of Circuits using Data-Dependent Power Management

“…Using these same principles, different precomputation architectures have been proposed in (Alidina et al 1994 …”

“…To obtain reduction in power with marginal increases in circuit area and delay, 91 and 92 have to be significantly less complex than I. The precomputation architecture of Figure 2 ensures this by making 91 and 92 depend on significantly fewer inputs than f. Methods to automatically determine the precomputation logic of a circuit are described in (Alidina et al 1994).…”

“…At the logic level, some shutdown techniques, such as precomputation (Alidina, Monteiro, Devadas, Ghosh & Papaefthymiou 1994), guarded evaluation (Tiwari, Ashar & Malik 1995) and gated-clockfinite state machines (Benini, Siegel & Micheli 1996), have been proposed recently and are among the most efficient power optimization techniques at this design level. These techniques are named data-dependent power management techniques as power management is achieved on a clock-cycle basis, function of the input conditions at the beginning of each clock cycle.…”

“…The precomputation method (Alidina et al 1994) adds a simple combinational circuit (the precomputation logic) to the original circuit. Under certain input conditions, the precomputation logic disables the loading of all or a subset of the input registers.…”