Power dissipation has recently emerged as one the most critical design constraints. Data-dependent power management techniques are among the most effective for power reduction. Depending on some input conditions, the clock driving some of the registers in the circuit is inhibited, thus reducing the switching activity in the fanout of those registers.The use of data-dependent power management techniques creates some interesting testability problems. The signals used to inhibit the clock can dramatically reduce the observability of the nodes in the circuit. In this paper, we first describe an approach for the complete testing of power-optimized circuits using these techniques. We then present results that show that using state-of-the-art techniques, ATPG for the power managed circuit is not significantly more difficult than for the original circuit.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.