Precision of synaptic weights programmed in phase-change memory devices for deep learning inference

Nandakumar, S. R.; Boybat, Irem; Han, Jin‐Ping; Ambrogio, Stefano; Adusumilli, Praneet; Bruce, Robert L.; BrightSky, M.; Rasch, Malte J.; Gallo, Manuel Le; Sebastian, Abu

doi:10.1109/iedm13553.2020.9371990

Cited by 25 publications

(22 citation statements)

References 5 publications

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“…2(d) for 16 distinct levels. The analog nature of the device, however, allows the encoding of more levels, the only limit being ADC precision and allowable programming time [35], [36].…”

Section: Unit Cell and Array Designmentioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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“…2(d) for 16 distinct levels. The analog nature of the device, however, allows the encoding of more levels, the only limit being ADC precision and allowable programming time [35], [36].…”

Section: Unit Cell and Array Designmentioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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“…Another contributor to programming inaccuracy is 1/f read noise [16], [17] which is not considered in this study. Recent work by Nandakumar et al show that the achievable programming precision will eventually be limited by the read noise [18].…”

Section: Simulation Resultsmentioning

confidence: 99%

Accurate Weight Mapping in a Multi-Memristive Synaptic Unit

Martemucci

Kersting

Khaddam-Aljameh

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In-memory computing using memristive devices is a promising non-von Neumann approach for making energyefficient deep learning inference hardware. Synaptic units comprising one or more memristive devices organized in a crossbar configuration are capable of performing the matrix-vector multiply operations in place by exploiting the Kirchhoff's circuits laws. In this paper, we propose a weight mapping algorithm to efficiently program such a synaptic unit comprising multiple phase change memory (PCM) devices to target conductance values. To evaluate the programming scheme, a simulator based on the measured programming characteristics of 10,000 PCM devices is developed. It is shown that the synaptic unit can be programmed reliably without significant overhead in programming time or energy compared to a unit comprising a single PCM device, while gaining resilience to device-level non-idealities and yield. The algorithm is experimentally verified on a prototype PCM unit cell fabricated in the 90nm CMOS technology node.

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“…For mapping the sliced weight matrix W to the PCM crossbar array, each weight slice is mapped to a differential PCM pair [34]. We assume a closed loop iterative programming with a read delay t 0 of 25 s and maximum conductance range G max of 25 μS [35]. Hence, each weight slice range r s_W is linearly mapped to the conductance range to obtain target conductance values G T .…”

Section: Pcm Modelmentioning

confidence: 99%

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

Gallo

Nandakumar

Ciric

et al. 2022

Neuromorph. Comput. Eng.

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In-memory computing is a promising non-von Neumann approach to perform certain computational tasks efﬁciently within memory devices by exploiting their physical attributes. However, the computational accuracy achieved with this approach has been rather low, owing to signiﬁcant inter-device variability and inhomogeneity across an array as well as intra-device variability and randomness from the analog memory devices. Bit slicing, a technique for constructing a high precision processor from several modules of lower precision, is a promising approach for overcoming this accuracy limitation. However, a systematic study to assess the precision ultimately achieved by bit slicing with analog in-memory computing has so far been lacking. In this work, we assess the computational error from bit slicing when performing in-memory matrix-vector multiplications. Using accurate models of phase-change memory crossbar arrays, we demonstrate that unlike in digital processors where bit slicing is used to extend the dynamic range of the number representation, bit slicing with in-memory computing should aim at minimizing the error from the analog matrix representation through averaging within a given dynamic range. The results are validated using a prototype phase-change memory chip and the impact on the neural network inference accuracy on CIFAR-10 and ImageNet benchmarks is evaluated.

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Precision of synaptic weights programmed in phase-change memory devices for deep learning inference

Cited by 25 publications

References 5 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Accurate Weight Mapping in a Multi-Memristive Synaptic Unit

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

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Precision of synaptic weights programmed in phase-change memory devices for deep learning inference

Cited by 25 publications

References 5 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Accurate Weight Mapping in a Multi-Memristive Synaptic Unit

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

Contact Info

Product

Resources

About

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs