Practical techniques to reduce skew and its variations in buffered clock networks

Venkataraman, Ganesh; Jayakumar, Nikhil; Hu, Jiang; Khatri, Sunil P.

doi:10.1109/iccad.2005.1560135

Cited by 36 publications

(74 citation statements)

References 16 publications

(32 reference statements)

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“…From the experimental results of [1][2][3][4], we can see that the methods of [2] reports the maximum reduction in skew variability with minimal increase in wirelength. So, we compare the efficacy of our method with the methods of [2].…”

Section: Resultsmentioning

confidence: 98%

“…This method has the advantage that every link insertion considers the effects of all the previously inserted links, unlike the methods of [1][2][3]. However, the method of [4] suffers from the serious disadvantage that the runtime is very high even for clock networks of relatively small size.…”

Section: Drawbacks Of Statistical Link Insertion Of [4]mentioning

confidence: 99%

“…The unwanted skew in the clock network is becoming a significant portion of the total clock time period, thereby limiting the speed and performance of the chip. The link-based CDNs proposed in [1][2][3] is a promising approach to reduce the skew variability in which cross-links are inserted in a given clock tree at appropriate locations. The cross links increase the correlation between the different sink delays which typically results in reduced skew variability.…”

Section: Introductionmentioning

confidence: 99%

“…The link selection schemes of [1][2][3] select the set of links to be inserted in a single step and then add all the links at the same time. Hence, we will refer to all these methods as one-step link insertion methods for the rest of this paper.…”

Section: Introductionmentioning

confidence: 99%

“…Recent works on link based non-tree CDN [1][2][3][4] propose cross-link insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values.…”

mentioning

confidence: 99%

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Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction

Rajaram

Pan

7th International Symposium on Quality Electronic Design (ISQED'06)

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With the advent of sub-100nm VLSI technologies, variation effects greatly increase the unwanted skew in Clock Distribution Networks (CDNs), thereby reducing the performance of the chip. Recent works on link based non-tree CDN [1][2][3][4] propose cross-link insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values. Also, the methods of [1-3] ignore the interaction between the different links while selecting the links for insertion. The method of [4] attempts to overcome this drawback using a statistical link insertion methodology. However, [4] is very slow even for relatively small circuits. In this paper, we propose a fast link insertion methodology which does not require selecting empirical parameters for link insertion. Our method also incrementally considers the effect of previously inserted links before choosing the next link. SPICE based Monte Carlo simulations show that our approach obtains comparable skew reduction to that of the existing approaches while drastically reducing the time taken to obtain a good link-based non-tree CDN.

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Section: Resultsmentioning

confidence: 98%

Section: Drawbacks Of Statistical Link Insertion Of [4]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction

Rajaram

Pan

7th International Symposium on Quality Electronic Design (ISQED'06)

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Design of robust signal and clock networks

Panitz

Olbrich

Barke

et al. 2007

Proc Appl Math and Mech

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As technology scales down into the nanometer region new design challenges emerge. Wire delays become the performance bottleneck in VLSI circuits. Copper is introduced as new wiring material because of its low sheet resistivity, hence low signal propagation delay. The main defect mechanism shifts from shorts to opens due to the different manufacturing process for copper wires. Open defects limit functional yield. Parametric yield decreases because of timing uncertainties emerging from manufacturing variation. Clock skew variation becomes critical because it may shorten the cycle length of the critical path. The variation of signal nets has to be considered simultaneously avoiding overly pessimistic designs. Design techniques which reduce the variation of design parameters avoid over design and increase parametric yield.Whereas tree topologies have been applied due to their minimal wire length, the application of generic routing graphs provides multiple paths to specific sinks. Multiple paths from source to sink increase the robustness against open defects and smoothes the effect of variation. New design techniques applying loops in VLSI wiring networks are the topic of this abstract.Millions of signal communication networks have to be designed on an integrated circuit (IC). Those networks can be classified according to their application. Signal nets connect a driving cell to a plurality of receiving cells. The ports of the cells are referred to as terminals and their physical representations are called pin. If the load of the driving cell is beyond its driving capabilities due to the large fan-out or wire length of the net, repeaters will be inserted and a repeater network is created. A repeater network consists of different nets that propagate the same signal or its inverse. A clock signal synchronizes the whole design. It is distributed via the clock network to all synchronous storage elements in a clock domain.There are four major trends that drive the development of IC circuit design in general and especially the design of onchip communication networks. With the integration of more and more devices per unit area and the demand for higher clock frequencies it is important to minimize the power dissipation and wire congestion on the chip. Additionally, the clock frequency is a constraint and yield is a maximization objective. A decade ago these objectives were adressed by applying routing trees as net topologies. With decreasing feature sizes trees have to be reconsidered because other topologies offer advantages. Topologies containing loops offer some robustness against opens. Additionally, an averaging effect can be exploited if the signal is propagated via multiple signal paths. If the signal arrives early on the fast path and late on the slow path, the arrival time of the signal is averaged. Therefore, loop topologies help to increase functional and parametric yield.The main advantage of trees is their minimal wire length (WL). Topologies containing loops always have an increased WL compared to trees. Extre...

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A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield

Liu

Kahng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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Practical techniques to reduce skew and its variations in buffered clock networks

Cited by 36 publications

References 16 publications

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction

Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction

Design of robust signal and clock networks

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield

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