In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.
Non-tree routing experiences an increasing interest as technology scales into the nanometer range. Via and wire opens have become the main yield detractors considering random spot defects due to the additive manufacturing process of copper wires. Wiring networks containing loops offer some robustness against open defects which increases functional yield. State-of-the-art delay calculation enables the treatment of loops but does not provide an adequate solution for timing analysis in the presence of an open. If the delay in the presence of an open is not properly analyzed, a functional fail will be masked and replaced by a parametric fail which is only detectable applying delay testing. In this paper we present a new method to rapidly calculate the maximum delay if an open occurs in the net. For topologies consisting of non-adjacent loops we provide proof that the worst delay considering the Elmore delay metric can be found in 2N + 1 delay calculations, whereas N is the number of loops in the net.
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