Practical System-on-Chip Repeater Design With Hybrid Meta-Heuristic Techniques

Teh, Eng Keong; Zawawi, Mohamad Adzhar Md; Mohamed, Mohamed Fauzi Packeer; Isa, Nor Ashidi Mat

doi:10.1109/access.2018.2866394

Cited by 4 publications

(6 citation statements)

References 20 publications

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“…6. In a recent complex SoC, the amount of timing paths that require flop-repeaters can be large and up to hundred thousand of flop-repeaters may be needed [43]. Furthermore, these paths are driven by different clock domains from various source IPs to destination IPs.…”

Section: Recent Fc Clock Design Challengesmentioning

confidence: 99%

“…10. First, an optimum clock repeater recipe will be identified using metaheuristic technique as proposed in our previous work [43], where a Genetic Algorithm (GA) based flow will perform global search through auto mixing and matching the input variables (aka "Genes") such as repeater types, wire layer/width/spacing, and repeater interval distances to perform layout constructions (aka "reproduction), and performance analysis (aka "Selection"). Based on the data paths information provided by logic designers, partitions physical location provided by FC floorplan, and the repeater latency recommended by the GA based recipe finder flow, critical FC timing paths will be identified, and higher weightage will be applied on the cost of clock divergence point of these paths during top level Steiner tree synthesis later.…”

Section: A Hybrid Global Clock Trunkmentioning

confidence: 99%

“…(1) Lookup Table (LUT) of latency per distance for the best know clock repeater recipe, which defines repeater types, metal layers, interval distance, and shielding that produce the global optimized QoR, as covered in our previous GA based HMH flow [43]. (2) A computational geometry technique base fast globalroute technique.…”

Section: B Fast Heuristic Flowmentioning

confidence: 99%

“…Different SoCs may have different priorities on PPA. To solve this multi-objective problem, a cost based mathematic algorithm, which is like our previous work [43], is used for rank-based selection. We can use a simple method to aggregate all the criteria into one criterion using a weighted summation [65], as in formula (10).…”

Section: Exact Algorithm For Dead Lock Solving and Selectionmentioning

confidence: 99%

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Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

et al. 2021

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This paper recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques proposed in the prior arts are no longer practical or enough. With that, we introduce a flexible FC Clock network topology and a synthesis algorithm that utilize a hybrid meta-heuristic technique to search for near optimum solution in shorter turn-around time. Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.INDEX TERMS system-on-a-chip (SoC), clock distribution, deep sub-micrometer, artificial intelligence, hybrid meta-heuristic.

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Section: Recent Fc Clock Design Challengesmentioning

confidence: 99%

Section: A Hybrid Global Clock Trunkmentioning

confidence: 99%

Section: B Fast Heuristic Flowmentioning

confidence: 99%

Section: Exact Algorithm For Dead Lock Solving and Selectionmentioning

confidence: 99%

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Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

et al. 2021

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“…Cloud has more service components among its networks. In [10], proposed a new architecture for the cloud computing based on service scheduling in the multiple cloud virtual environment.…”

Section: Literature Surveymentioning

confidence: 99%

A Survey on Service Level Components in Big-Cloud-IoT Systems with Hybrid Meta-heuristic Techniques

Yin¹,

Chen

2020

International Journal of Advanced Information and Communication Technology

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Big data is one such technology. When we receive huge volume of data, there will be high demand in processing the huge data. It can also be said challenging task in big data processing. The increases in IoT devices in the network system collect more data to be processed in centralized devices called cloud storage. Every big data is processed and stored in the cloud. To overcome the performance and latency issues in large data computation, big cloud processing system uses edge computing in it. One of the key components of IoT is edge computing. We combine big data with cloud and edge computing in this paper as hybrid edge computing system. In the edge computing system, huge number of IoT devices computes services in its nearby network edge. Data sharing and transmission between the various service components may affect performance of the system. The main aim of this research article is to reduce the delay in data transfer between the components. This optimization goal is achieved by new Hybrid Meta-heuristic optimization (HMeO) algorithm. New HMeO algorithm designed for IoT devices to deploy the service components. MHO model is design to optimize the process by selecting the edge computing with minimum latency. Our proposed HMeO algorithm is compared with existing genetic algorithm and ant colony algorithm. The result shows HMeO algorithm provides more performance and efficient in in-depth data analysing and locating the component in big databased cloud environment.

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