Practical and secure PCM systems by online detection of malicious write streams

Qureshi, Moinuddin K.; Seznec, André; Lastras, Luis A.; Franceschini, Michele

doi:10.1109/hpca.2011.5749753

Cited by 69 publications

(49 citation statements)

References 10 publications

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“…Repeated address attack: This issues repeated writes to a physical address (PA) to make it fail. By changing the write-pattern, several variants of this attack can be created [10]. 2.…”

Section: Techniques For Mitigating Write Attacks Techniques For Reducmentioning

confidence: 99%

“…Qureshi et al [10] note that while lowering the rate of WL leaves the system vulnerable to attacks, increasing the WL rate write overhead greatly, even for benign processes. Hence, they propose that the WL rate should be decided by the nature of memory access stream such that it is low/high for common/attacking programs, respectively.…”

Section: Detecting Write Attacksmentioning

confidence: 99%

“…Hence, they use a frequency-based replacement policy which records the number of writes to each entry. In this policy, an entry with the lowest (possibly zero) number of writes, except a newly installed entry, is Determining WL rate for normal and attack-like write streams [10]. N shows the number of lines in the memory.…”

Section: Detecting Write Attacksmentioning

confidence: 99%

See 2 more Smart Citations

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

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Due to their high-density and near-zero leakage power consumption, non-volatile memories (NVMs) are promising candidates for designing future memory systems. However, compared to conventional memories, NVMs also face more severe security threats, e.g., the limited write endurance of NVMs makes them vulnerable to write attacks. Also, the nonvolatility of NVMs allows the data to persist even after power-off, which can be accessed by a malicious agent. Further, encryption endangers NVM lifetime and performance by reducing the efficacy of redundant write avoidance techniques. In this paper, we present a survey of techniques for improving security of NVM-based memories by addressing the aforementioned challenges. We highlight the key ideas of the techniques along with their similarities and differences. This paper is expected to be useful for researchers and practitioners in the area of memory and system security.

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“…Repeated address attack: This issues repeated writes to a physical address (PA) to make it fail. By changing the write-pattern, several variants of this attack can be created [10]. 2.…”

Section: Techniques For Mitigating Write Attacks Techniques For Reducmentioning

confidence: 99%

Section: Detecting Write Attacksmentioning

confidence: 99%

See 1 more Smart Citation

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

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“…Wear leveling techniques that aim to evenly distribute write activities include hot/cold line shifting and segment swapping [5], randomized mapping such as StartGap [17] and Security Refresh [18], and adaptive wear leveling with online attack detector [19]. To defend against malicious attacks, randomized approaches have been proposed to randomly distribute writes [17][18][19][20].…”

Section: Related Workmentioning

confidence: 99%

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Wang

Guan

et al. 2015

Computing

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In embedded systems, especially battery-driven mobile devices, energy is one of the most critical performance metrics. Due to its high density and low standby power, phase change memory (PCM), an emerging non-volatile memory device, is becoming a promising dynamic random access memory (DRAM) alternative. Recent studies have proposed the hybrid main memory architecture integrating both PCM and DRAM to fully take advantage of the properties of both memories. However, the low power performance of PCM in the hybrid main memory architecture has not been fully explored. Therefore, it becomes an interesting problem to utilize PCM and DRAM as hybrid main memory for energy optimization in embedded systems. In this paper, we present an energy optimization technique for hybrid main memory architecture. The objective is to fully utilize PCM to reduce the energy consumption while ensuring that the real-time performance of applications are guaranteed. We propose a two-phase approach to solve hybrid main memory address mapping problem. In the first phase, we calculate energy and time cost for each address based on the task models. Then the applications can be modeled as data-flow graph nodes, and different access times will associate with different energy consumption. In the second phase, for different memory types and the given timing constraint, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal solution. The 123 G. Wang et al.ILP model can map a proper memory type for each address such that the total energy consumption can be minimized while the timing constraint is satisfied. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on an ARM-based simulator. The experimental results show that our method can effectively reduce the energy consumption with the least system cost compared with the previous work.

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“…The authors of [138] offered a countermeasure for the PCM write threat according to which either the number of write operations is reduced or a "wear-leveling" is used to "write uniformly". A few examples of wear-leveling methods include the randomized region-based Start-Gap [139], the multi-level Security Refresh [140], and Online Attack Detection [141]. These methods suffer from high write or extra hardware overheads due to their frequent need in swapping data for speeding up the process of remapping logical to physical addresses.…”

Section: Emerging Memory Securitymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Practical and secure PCM systems by online detection of malicious write streams

Abstract: International audienc

Cited by 69 publications

References 10 publications

A Survey of Techniques for Improving Security of Non-volatile Memories

A Survey of Techniques for Improving Security of Non-volatile Memories

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

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