PowerDAC: a single-chip audio DAC with a 70%-efficient power stage in 0.5 μm CMOS

Class-D Amplifier Power Stage With PWM Feedback Loop

“…The circuit operates at 3.3V supply voltage and the maximum unclipped power efficiency obtained with a 16 Ω load condition is 89.5%. It had been shown in [20] that the proposed design attains a comparable PSR performance, with much better THD results than the PowerDac design that was introduced in [17]. In this paper, the sources of harmonic distortion of the proposed design are identified, and verified with the simulation and measurement results shown in this section.…”

“…In this way, the design complexity of the digital PCM-to-PWM stage is greatly reduced, and the requirement of ADC in the feedback path is also eliminated. In fact, several PWM feedback techniques had been developed to improve the PSR of the half-bridge CDA power stage [17][18][19], however, the improvement made by these techniques is rather inadequate.…”

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“…Particularly, portable low-power VLSI system-on-a-chip applications like Hearing Aids require this type of signal modulation in order to extend battery life. Unfortunately, most existing CMOS solutions do not allow good-enough low-voltage compatibility for real single battery cell operation (down to 1.1V) [1,2,3], requiring supply multipliers which tend to decrease power efficiency, and increase both external components and Si area overhead as well. Other reported proposals make extensive usage of resistors or bipolar devices [4,5].…”

Class-D amplifier power stage with PWM feedback loop

“…In addition, the inherent time delay of the ADC would also affect the overall stability of the amplifier system [13]. Till date, there are not many reported solutions [72][73][74][75][76][77][78] that had fully addressed the PSRR rejection problems for digital switching amplifier. output power which is four times higher than its half bridge counterpart [2,3].…”